Lines Matching defs:imxdi
97 * struct imxdi_dev - private imxdi rtc data
170 static void di_write_busy_wait(const struct imxdi_dev *imxdi, u32 val,
174 writel(val, imxdi->ioaddr + reg);
183 static void di_report_tamper_info(struct imxdi_dev *imxdi, u32 dsr)
187 dtcr = readl(imxdi->ioaddr + DTCR);
189 dev_emerg(&imxdi->pdev->dev, "DryIce tamper event detected\n");
192 dev_emerg(&imxdi->pdev->dev, "%sVoltage Tamper Event\n",
196 dev_emerg(&imxdi->pdev->dev, "%s32768 Hz Clock Tamper Event\n",
200 dev_emerg(&imxdi->pdev->dev, "%sTemperature Tamper Event\n",
204 dev_emerg(&imxdi->pdev->dev,
209 dev_emerg(&imxdi->pdev->dev, "%sExternal Boot Tamper Event\n",
213 dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper A Event\n",
217 dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper B Event\n",
221 dev_emerg(&imxdi->pdev->dev, "%sWire-mesh Tamper Event\n",
225 dev_emerg(&imxdi->pdev->dev,
230 dev_emerg(&imxdi->pdev->dev, "%sTimer-counter Overflow Event\n",
234 static void di_what_is_to_be_done(struct imxdi_dev *imxdi,
237 dev_emerg(&imxdi->pdev->dev, "Please cycle the %s power supply in order to get the DryIce/RTC unit working again\n",
241 static int di_handle_failure_state(struct imxdi_dev *imxdi, u32 dsr)
245 dev_dbg(&imxdi->pdev->dev, "DSR register reports: %08X\n", dsr);
248 di_report_tamper_info(imxdi, dsr);
250 dcr = readl(imxdi->ioaddr + DCR);
254 di_what_is_to_be_done(imxdi, "battery");
261 di_what_is_to_be_done(imxdi, "main");
266 static int di_handle_valid_state(struct imxdi_dev *imxdi, u32 dsr)
269 di_write_busy_wait(imxdi, DCAMR_UNSET, DCAMR);
270 di_write_busy_wait(imxdi, 0, DCALR);
274 di_write_busy_wait(imxdi, DSR_CAF, DSR);
279 static int di_handle_invalid_state(struct imxdi_dev *imxdi, u32 dsr)
287 di_write_busy_wait(imxdi, 0x00000000, DTCR);
289 di_write_busy_wait(imxdi, DCR_TDCSL, DCR);
291 sec = readl(imxdi->ioaddr + DTCMR);
293 dev_warn(&imxdi->pdev->dev,
300 dcr = readl(imxdi->ioaddr + DCR);
304 di_what_is_to_be_done(imxdi, "battery");
308 di_what_is_to_be_done(imxdi, "main");
324 di_write_busy_wait(imxdi, DSR_NVF, DSR);
326 di_write_busy_wait(imxdi, DSR_TCO, DSR);
328 di_write_busy_wait(imxdi, dcr | DCR_TCE, DCR);
330 di_write_busy_wait(imxdi, sec, DTCMR);
333 return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR));
336 static int di_handle_invalid_and_failure_state(struct imxdi_dev *imxdi, u32 dsr)
347 dcr = __raw_readl(imxdi->ioaddr + DCR);
360 di_what_is_to_be_done(imxdi, "battery");
365 di_what_is_to_be_done(imxdi, "main");
371 di_write_busy_wait(imxdi, 0x00000000, DTCR);
374 di_write_busy_wait(imxdi, dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD |
378 dsr = readl(imxdi->ioaddr + DSR);
381 dev_warn(&imxdi->pdev->dev,
390 di_write_busy_wait(imxdi, DSR_SVF, DSR);
393 dsr = readl(imxdi->ioaddr + DSR);
395 dev_crit(&imxdi->pdev->dev,
398 di_what_is_to_be_done(imxdi, "battery");
406 return di_handle_invalid_state(imxdi, dsr);
409 static int di_handle_state(struct imxdi_dev *imxdi)
414 dsr = readl(imxdi->ioaddr + DSR);
418 dev_warn(&imxdi->pdev->dev, "Invalid stated unit detected\n");
419 rc = di_handle_invalid_state(imxdi, dsr);
422 dev_warn(&imxdi->pdev->dev, "Failure stated unit detected\n");
423 rc = di_handle_failure_state(imxdi, dsr);
426 dev_warn(&imxdi->pdev->dev,
428 rc = di_handle_invalid_and_failure_state(imxdi, dsr);
431 dev_notice(&imxdi->pdev->dev, "Unlocked unit detected\n");
432 rc = di_handle_valid_state(imxdi, dsr);
441 static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
445 spin_lock_irqsave(&imxdi->irq_lock, flags);
446 writel(readl(imxdi->ioaddr + DIER) | intr,
447 imxdi->ioaddr + DIER);
448 spin_unlock_irqrestore(&imxdi->irq_lock, flags);
454 static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
458 spin_lock_irqsave(&imxdi->irq_lock, flags);
459 writel(readl(imxdi->ioaddr + DIER) & ~intr,
460 imxdi->ioaddr + DIER);
461 spin_unlock_irqrestore(&imxdi->irq_lock, flags);
471 static void clear_write_error(struct imxdi_dev *imxdi)
475 dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
478 writel(DSR_WEF, imxdi->ioaddr + DSR);
482 if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
486 dev_err(&imxdi->pdev->dev,
496 static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
502 mutex_lock(&imxdi->write_mutex);
505 di_int_enable(imxdi, DIER_WCIE);
507 imxdi->dsr = 0;
510 writel(val, imxdi->ioaddr + reg);
513 ret = wait_event_interruptible_timeout(imxdi->write_wait,
514 imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
519 dev_warn(&imxdi->pdev->dev,
525 if (imxdi->dsr & DSR_WEF) {
526 clear_write_error(imxdi);
531 mutex_unlock(&imxdi->write_mutex);
541 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
544 now = readl(imxdi->ioaddr + DTCMR);
556 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
560 dcr = readl(imxdi->ioaddr + DCR);
561 dsr = readl(imxdi->ioaddr + DSR);
566 di_what_is_to_be_done(imxdi, "battery");
571 di_what_is_to_be_done(imxdi, "main");
577 rc = di_write_wait(imxdi, 0, DTCLR);
581 rc = di_write_wait(imxdi, rtc_tm_to_time64(tm), DTCMR);
585 return di_write_wait(imxdi, readl(imxdi->ioaddr + DCR) | DCR_TCE, DCR);
591 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
594 di_int_enable(imxdi, DIER_CAIE);
596 di_int_disable(imxdi, DIER_CAIE);
607 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
610 dcamr = readl(imxdi->ioaddr + DCAMR);
614 alarm->enabled = (readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
617 mutex_lock(&imxdi->write_mutex);
620 alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
622 mutex_unlock(&imxdi->write_mutex);
632 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
636 rc = di_write_wait(imxdi, rtc_tm_to_time64(&alarm->time), DCAMR);
641 di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
643 di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
661 struct imxdi_dev *imxdi = dev_id;
665 dier = readl(imxdi->ioaddr + DIER);
666 dsr = readl(imxdi->ioaddr + DSR);
679 di_int_disable(imxdi, DIER_SVIE);
681 di_report_tamper_info(imxdi, dsr);
691 if (list_empty_careful(&imxdi->write_wait.head))
697 di_int_disable(imxdi, DIER_WCIE);
700 imxdi->dsr |= dsr;
702 wake_up_interruptible(&imxdi->write_wait);
712 di_int_disable(imxdi, DIER_CAIE);
715 schedule_work(&imxdi->work);
728 struct imxdi_dev *imxdi = container_of(work,
732 di_write_wait(imxdi, DSR_CAF, DSR);
735 rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
743 struct imxdi_dev *imxdi;
747 imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
748 if (!imxdi)
751 imxdi->pdev = pdev;
753 imxdi->ioaddr = devm_platform_ioremap_resource(pdev, 0);
754 if (IS_ERR(imxdi->ioaddr))
755 return PTR_ERR(imxdi->ioaddr);
757 spin_lock_init(&imxdi->irq_lock);
770 init_waitqueue_head(&imxdi->write_wait);
772 INIT_WORK(&imxdi->work, dryice_work);
774 mutex_init(&imxdi->write_mutex);
776 imxdi->rtc = devm_rtc_allocate_device(&pdev->dev);
777 if (IS_ERR(imxdi->rtc))
778 return PTR_ERR(imxdi->rtc);
780 imxdi->clk = devm_clk_get(&pdev->dev, NULL);
781 if (IS_ERR(imxdi->clk))
782 return PTR_ERR(imxdi->clk);
783 rc = clk_prepare_enable(imxdi->clk);
792 writel(0, imxdi->ioaddr + DIER);
794 rc = di_handle_state(imxdi);
799 IRQF_SHARED, pdev->name, imxdi);
806 IRQF_SHARED, pdev->name, imxdi);
812 platform_set_drvdata(pdev, imxdi);
814 imxdi->rtc->ops = &dryice_rtc_ops;
815 imxdi->rtc->range_max = U32_MAX;
817 rc = rtc_register_device(imxdi->rtc);
824 clk_disable_unprepare(imxdi->clk);
831 struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
833 flush_work(&imxdi->work);
836 writel(0, imxdi->ioaddr + DIER);
838 clk_disable_unprepare(imxdi->clk);