Lines Matching refs:ctrl
94 u8 ctrl[DS1305_CONTROL_LEN];
146 buf[1] = ds1305->ctrl[0];
149 if (ds1305->ctrl[0] & DS1305_AEI0)
159 ds1305->ctrl[0] = buf[1];
264 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
281 ds1305->ctrl, sizeof(ds1305->ctrl));
285 alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
286 alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
316 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
343 if (ds1305->ctrl[0] & DS1305_AEI0) {
344 ds1305->ctrl[0] &= ~DS1305_AEI0;
347 buf[1] = ds1305->ctrl[0];
370 ds1305->ctrl[0] |= DS1305_AEI0;
373 buf[1] = ds1305->ctrl[0];
388 /* ctrl[2] is treated as read-only; no locking needed */
389 if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
390 switch (ds1305->ctrl[2] & 0x0c) {
400 switch (ds1305->ctrl[2] & 0x03) {
443 /* lock to protect ds1305->ctrl */
450 ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
451 ds1305->ctrl[1] = 0;
454 buf[1] = ds1305->ctrl[0];
472 * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
579 ds1305->ctrl, sizeof(ds1305->ctrl));
586 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
593 if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
597 if (ds1305->ctrl[2] == 0)
603 if (ds1305->ctrl[0] & DS1305_WP) {
606 ds1305->ctrl[0] &= ~DS1305_WP;
609 buf[1] = ds1305->ctrl[0];
620 if (ds1305->ctrl[0] & DS1305_nEOSC) {
621 ds1305->ctrl[0] &= ~DS1305_nEOSC;
627 if (ds1305->ctrl[1]) {
628 ds1305->ctrl[1] = 0;
635 if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
636 ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
644 if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
645 ds1305->ctrl[0] |= DS1306_1HZ;
649 if (ds1305->ctrl[0] & DS1306_1HZ) {
650 ds1305->ctrl[0] &= ~DS1306_1HZ;
661 buf[1] = ds1305->ctrl[0];
662 buf[2] = ds1305->ctrl[1];
663 buf[3] = ds1305->ctrl[2];
671 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
687 /* register RTC ... from here on, ds1305->ctrl needs locking */