Lines Matching defs:rtc
16 #include <linux/rtc.h>
87 void (*update_mbus_timing)(struct armada38x_rtc *rtc);
88 u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
89 void (*clear_isr)(struct armada38x_rtc *rtc);
90 void (*unmask_interrupt)(struct armada38x_rtc *rtc);
104 static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
106 writel(0, rtc->regs + RTC_STATUS);
107 writel(0, rtc->regs + RTC_STATUS);
108 writel(val, rtc->regs + offset);
113 static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
117 reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
122 writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
125 static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
129 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
134 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
136 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
139 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
142 static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
144 return readl(rtc->regs + rtc_reg);
147 static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
152 rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
153 rtc->val_to_freq[i].freq = 0;
158 u32 value = rtc->val_to_freq[i].value;
160 while (rtc->val_to_freq[j].freq) {
161 if (rtc->val_to_freq[j].value == value) {
162 rtc->val_to_freq[j].freq++;
168 if (!rtc->val_to_freq[j].freq) {
169 rtc->val_to_freq[j].value = value;
170 rtc->val_to_freq[j].freq = 1;
173 if (rtc->val_to_freq[j].freq > max) {
175 max = rtc->val_to_freq[j].freq;
186 return rtc->val_to_freq[index_max].value;
189 static void armada38x_clear_isr(struct armada38x_rtc *rtc)
191 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
193 writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
196 static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
198 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
200 writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
203 static void armada8k_clear_isr(struct armada38x_rtc *rtc)
205 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
208 static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
210 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
215 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
218 spin_lock_irqsave(&rtc->lock, flags);
219 time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
220 spin_unlock_irqrestore(&rtc->lock, flags);
227 static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
231 reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
234 rtc_delayed_write(0, rtc, RTC_CONF_TEST);
236 rtc_delayed_write(0, rtc, RTC_TIME);
237 rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc,
239 rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
241 rtc->initialized = true;
246 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
251 if (!rtc->initialized)
252 armada38x_rtc_reset(rtc);
254 spin_lock_irqsave(&rtc->lock, flags);
255 rtc_delayed_write(time, rtc, RTC_TIME);
256 spin_unlock_irqrestore(&rtc->lock, flags);
263 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
265 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
266 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
269 spin_lock_irqsave(&rtc->lock, flags);
271 time = rtc->data->read_rtc_reg(rtc, reg);
272 val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
274 spin_unlock_irqrestore(&rtc->lock, flags);
284 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
285 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
286 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
291 spin_lock_irqsave(&rtc->lock, flags);
293 rtc_delayed_write(time, rtc, reg);
296 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
297 rtc->data->unmask_interrupt(rtc);
300 spin_unlock_irqrestore(&rtc->lock, flags);
308 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
309 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
312 spin_lock_irqsave(&rtc->lock, flags);
315 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
317 rtc_delayed_write(0, rtc, reg_irq);
319 spin_unlock_irqrestore(&rtc->lock, flags);
326 struct armada38x_rtc *rtc = data;
329 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
331 dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
333 spin_lock(&rtc->lock);
335 rtc->data->clear_isr(rtc);
336 val = rtc->data->read_rtc_reg(rtc, reg_irq);
338 rtc_delayed_write(0, rtc, reg_irq);
340 rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
342 spin_unlock(&rtc->lock);
351 rtc_update_irq(rtc->rtc_dev, 1, event);
400 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
404 spin_lock_irqsave(&rtc->lock, flags);
405 ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
406 spin_unlock_irqrestore(&rtc->lock, flags);
417 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
446 rtc_delayed_write(ccr, rtc, RTC_CCR);
488 .compatible = "marvell,armada-380-rtc",
492 .compatible = "marvell,armada-8k-rtc",
503 struct armada38x_rtc *rtc;
505 rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
507 if (!rtc)
510 rtc->data = of_device_get_match_data(&pdev->dev);
512 rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
514 if (!rtc->val_to_freq)
517 spin_lock_init(&rtc->lock);
519 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
520 rtc->regs = devm_ioremap_resource(&pdev->dev, res);
521 if (IS_ERR(rtc->regs))
522 return PTR_ERR(rtc->regs);
523 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
524 rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
525 if (IS_ERR(rtc->regs_soc))
526 return PTR_ERR(rtc->regs_soc);
528 rtc->irq = platform_get_irq(pdev, 0);
529 if (rtc->irq < 0)
530 return rtc->irq;
532 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
533 if (IS_ERR(rtc->rtc_dev))
534 return PTR_ERR(rtc->rtc_dev);
536 if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
537 0, pdev->name, rtc) < 0) {
539 rtc->irq = -1;
541 platform_set_drvdata(pdev, rtc);
543 if (rtc->irq != -1) {
545 rtc->rtc_dev->ops = &armada38x_rtc_ops;
551 rtc->rtc_dev->ops = &armada38x_rtc_ops_noirq;
555 rtc->data->update_mbus_timing(rtc);
557 rtc->rtc_dev->range_max = U32_MAX;
559 return rtc_register_device(rtc->rtc_dev);
566 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
568 return enable_irq_wake(rtc->irq);
577 struct armada38x_rtc *rtc = dev_get_drvdata(dev);
580 rtc->data->update_mbus_timing(rtc);
582 return disable_irq_wake(rtc->irq);
594 .name = "armada38x-rtc",