Lines Matching refs:val
501 s32 val;
505 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
506 if (val)
515 return val;
522 s32 val;
526 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
527 if (val < 0)
530 if (!status && val)
532 else if (status && val == status)
541 return val;
566 u32 val;
571 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
572 val |= Q6SS_CBCR_CLKEN;
573 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
576 val, !(val & Q6SS_CBCR_CLKOFF), 1,
589 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
599 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
600 val |= Q6SS_CBCR_CLKEN;
601 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
604 val, !(val & Q6SS_CBCR_CLKOFF), 1,
612 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
613 val |= Q6SS_CBCR_CLKEN;
614 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
617 val, !(val & Q6SS_CBCR_CLKOFF), 1,
625 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
626 val |= Q6SS_CBCR_CLKEN;
627 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
640 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
657 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
658 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
659 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
662 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
663 val |= Q6SS_CBCR_CLKEN;
664 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
668 val, !(val & Q6SS_CBCR_CLKOFF), 1,
676 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
677 val |= QDSP6v56_BHS_ON;
678 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
679 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
683 val |= QDSP6v56_LDO_BYP;
684 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
687 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
688 val &= ~QDSP6v56_CLAMP_QMC_MEM;
689 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
692 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
693 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
704 val = readl(qproc->reg_base + mem_pwr_ctl);
706 val |= BIT(i);
707 writel(val, qproc->reg_base + mem_pwr_ctl);
713 val |= readl(qproc->reg_base + mem_pwr_ctl);
717 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
718 val &= ~QDSP6v56_CLAMP_WL;
719 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
722 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
723 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
724 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
727 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
728 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
729 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
730 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
736 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
737 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
739 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
740 val |= Q6SS_L2DATA_SLP_NRET_N_2;
741 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
742 val |= Q6SS_L2DATA_SLP_NRET_N_1;
743 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
744 val |= Q6SS_L2DATA_SLP_NRET_N_0;
745 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
748 val &= ~Q6SS_CLAMP_IO;
749 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
752 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
753 val &= ~Q6SS_CORE_ARES;
754 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
757 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
758 val |= Q6SS_CLK_ENABLE;
759 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
762 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
763 val &= ~Q6SS_STOP_CORE;
764 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
785 unsigned int val;
789 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
790 if (!ret && val)
797 regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
798 val, 1000, HALT_ACK_TIMEOUT_US);
800 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
801 if (ret || !val)
1053 u32 val;
1065 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1066 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1068 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);