Lines Matching defs:reg_base
153 void __iomem *reg_base;
571 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
573 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
575 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
584 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
586 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
599 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
601 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
603 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
612 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
614 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
616 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
625 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
627 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
630 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
636 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
654 qproc->reg_base + QDSP6SS_STRAP_ACC);
657 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
659 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
662 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
664 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
667 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
676 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
678 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
679 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
684 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
687 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
689 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
693 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
704 val = readl(qproc->reg_base + mem_pwr_ctl);
707 writel(val, qproc->reg_base + mem_pwr_ctl);
713 val |= readl(qproc->reg_base + mem_pwr_ctl);
717 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
719 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
722 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
724 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
727 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
729 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
730 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
736 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
739 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
741 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
743 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
745 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
749 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
752 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
754 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
757 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
759 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
762 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
764 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
1065 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1068 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1483 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
1484 if (IS_ERR(qproc->reg_base))
1485 return PTR_ERR(qproc->reg_base);