Lines Matching defs:STM32_VREFBUF_CSR
20 #define STM32_VREFBUF_CSR 0x00
53 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
55 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
63 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val,
67 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
69 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
90 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
92 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
111 ret = readl_relaxed(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR;
132 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
134 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
154 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);