Lines Matching refs:shadow_regs
70 u8 shadow_regs[MAX8660_N_REGS]; /* as chip is write only */
80 u8 reg_val = (max8660->shadow_regs[reg] & mask) | val;
88 max8660->shadow_regs[reg] = reg_val;
101 u8 val = max8660->shadow_regs[MAX8660_OVER1];
127 u8 selector = max8660->shadow_regs[reg];
166 u8 selector = max8660->shadow_regs[MAX8660_MDTV2];
199 u8 val = max8660->shadow_regs[MAX8660_OVER2];
225 u8 selector = (max8660->shadow_regs[MAX8660_L12VCR] >> shift) & 0xf;
412 max8660->shadow_regs[MAX8660_OVER1] = 5;
424 max8660->shadow_regs[MAX8660_ADTV1] =
425 max8660->shadow_regs[MAX8660_ADTV2] =
426 max8660->shadow_regs[MAX8660_SDTV1] =
427 max8660->shadow_regs[MAX8660_SDTV2] = 0x1b;
428 max8660->shadow_regs[MAX8660_MDTV1] =
429 max8660->shadow_regs[MAX8660_MDTV2] = 0x04;
441 max8660->shadow_regs[MAX8660_OVER1] |= 1;
446 max8660->shadow_regs[MAX8660_OVER1] |= 4;
454 max8660->shadow_regs[MAX8660_OVER2] |= 2;
464 max8660->shadow_regs[MAX8660_OVER2] |= 4;