Lines Matching refs:bdma_chan
63 static int tsi721_bdma_ch_init(struct tsi721_bdma_chan *bdma_chan, int bd_num)
66 struct device *dev = bdma_chan->dchan.device->dev;
72 struct tsi721_device *priv = to_tsi721(bdma_chan->dchan.device);
75 tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d", bdma_chan->id);
87 bdma_chan->bd_num = bd_num;
88 bdma_chan->bd_phys = bd_phys;
89 bdma_chan->bd_base = bd_ptr;
91 tsi_debug(DMA, &bdma_chan->dchan.dev->device,
93 bdma_chan->id, bd_ptr, &bd_phys);
107 bdma_chan->bd_base = NULL;
111 bdma_chan->sts_phys = sts_phys;
112 bdma_chan->sts_base = sts_ptr;
113 bdma_chan->sts_size = sts_size;
115 tsi_debug(DMA, &bdma_chan->dchan.dev->device,
117 bdma_chan->id, sts_ptr, &sts_phys, sts_size);
127 bdma_chan->regs + TSI721_DMAC_DPTRH);
129 bdma_chan->regs + TSI721_DMAC_DPTRL);
133 bdma_chan->regs + TSI721_DMAC_DSBH);
135 bdma_chan->regs + TSI721_DMAC_DSBL);
137 bdma_chan->regs + TSI721_DMAC_DSSZ);
141 bdma_chan->regs + TSI721_DMAC_INT);
143 ioread32(bdma_chan->regs + TSI721_DMAC_INT);
150 idx = TSI721_VECT_DMA0_DONE + bdma_chan->id;
153 priv->msix[idx].irq_name, (void *)bdma_chan);
156 tsi_debug(DMA, &bdma_chan->dchan.dev->device,
158 bdma_chan->id);
162 idx = TSI721_VECT_DMA0_INT + bdma_chan->id;
165 priv->msix[idx].irq_name, (void *)bdma_chan);
168 tsi_debug(DMA, &bdma_chan->dchan.dev->device,
170 bdma_chan->id);
173 bdma_chan->id].vector,
174 (void *)bdma_chan);
183 bdma_chan->bd_base = NULL;
189 bdma_chan->sts_base = NULL;
197 iowrite32(TSI721_DMAC_CTL_INIT, bdma_chan->regs + TSI721_DMAC_CTL);
198 ioread32(bdma_chan->regs + TSI721_DMAC_CTL);
199 bdma_chan->wr_count = bdma_chan->wr_count_next = 0;
200 bdma_chan->sts_rdptr = 0;
206 static int tsi721_bdma_ch_free(struct tsi721_bdma_chan *bdma_chan)
210 struct tsi721_device *priv = to_tsi721(bdma_chan->dchan.device);
213 if (!bdma_chan->bd_base)
217 ch_stat = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
222 iowrite32(TSI721_DMAC_CTL_INIT, bdma_chan->regs + TSI721_DMAC_CTL);
227 bdma_chan->id].vector, (void *)bdma_chan);
229 bdma_chan->id].vector, (void *)bdma_chan);
234 dma_free_coherent(bdma_chan->dchan.device->dev,
235 (bdma_chan->bd_num + 1) * sizeof(struct tsi721_dma_desc),
236 bdma_chan->bd_base, bdma_chan->bd_phys);
237 bdma_chan->bd_base = NULL;
240 dma_free_coherent(bdma_chan->dchan.device->dev,
241 bdma_chan->sts_size * sizeof(struct tsi721_dma_sts),
242 bdma_chan->sts_base, bdma_chan->sts_phys);
243 bdma_chan->sts_base = NULL;
248 tsi721_bdma_interrupt_enable(struct tsi721_bdma_chan *bdma_chan, int enable)
253 bdma_chan->regs + TSI721_DMAC_INT);
254 ioread32(bdma_chan->regs + TSI721_DMAC_INT);
257 bdma_chan->regs + TSI721_DMAC_INTE);
260 iowrite32(0, bdma_chan->regs + TSI721_DMAC_INTE);
263 bdma_chan->regs + TSI721_DMAC_INT);
268 static bool tsi721_dma_is_idle(struct tsi721_bdma_chan *bdma_chan)
272 sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
276 void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan)
279 iowrite32(0, bdma_chan->regs + TSI721_DMAC_INTE);
280 if (bdma_chan->active)
281 tasklet_hi_schedule(&bdma_chan->tasklet);
294 struct tsi721_bdma_chan *bdma_chan = ptr;
296 if (bdma_chan->active)
297 tasklet_hi_schedule(&bdma_chan->tasklet);
303 static void tsi721_start_dma(struct tsi721_bdma_chan *bdma_chan)
305 if (!tsi721_dma_is_idle(bdma_chan)) {
306 tsi_err(&bdma_chan->dchan.dev->device,
308 bdma_chan->id);
312 if (bdma_chan->wr_count == bdma_chan->wr_count_next) {
313 tsi_err(&bdma_chan->dchan.dev->device,
315 bdma_chan->id, task_pid_nr(current));
319 tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d (wrc=%d) %d",
320 bdma_chan->id, bdma_chan->wr_count_next,
323 iowrite32(bdma_chan->wr_count_next,
324 bdma_chan->regs + TSI721_DMAC_DWRCNT);
325 ioread32(bdma_chan->regs + TSI721_DMAC_DWRCNT);
327 bdma_chan->wr_count = bdma_chan->wr_count_next;
372 static void tsi721_dma_tx_err(struct tsi721_bdma_chan *bdma_chan,
379 list_move(&desc->desc_node, &bdma_chan->free_list);
385 static void tsi721_clr_stat(struct tsi721_bdma_chan *bdma_chan)
392 srd_ptr = bdma_chan->sts_rdptr;
393 sts_ptr = bdma_chan->sts_base;
400 srd_ptr %= bdma_chan->sts_size;
404 iowrite32(srd_ptr, bdma_chan->regs + TSI721_DMAC_DSRP);
405 bdma_chan->sts_rdptr = srd_ptr;
412 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
425 if (!tsi721_dma_is_idle(bdma_chan)) {
427 bdma_chan->id);
440 rd_idx = ioread32(bdma_chan->regs + TSI721_DMAC_DRDCNT);
441 rd_idx %= (bdma_chan->bd_num + 1);
443 idx = bdma_chan->wr_count_next % (bdma_chan->bd_num + 1);
444 if (idx == bdma_chan->bd_num) {
451 bdma_chan->id, rd_idx, idx);
456 bdma_chan->id, i, desc->sg_len,
461 bdma_chan->id, i);
479 bdma_chan->id, bcount);
487 bdma_chan->id, i);
493 bd_ptr = &((struct tsi721_dma_desc *)bdma_chan->bd_base)[idx];
501 bdma_chan->id, bd_ptr, desc->destid, desc->rio_addr);
507 if (++idx == bdma_chan->bd_num) {
518 bdma_chan->id, bcount);
527 bdma_chan->wr_count_next += add_count;
532 static void tsi721_advance_work(struct tsi721_bdma_chan *bdma_chan,
537 tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d", bdma_chan->id);
539 if (!tsi721_dma_is_idle(bdma_chan))
546 if (!desc && !bdma_chan->active_tx && !list_empty(&bdma_chan->queue)) {
547 desc = list_first_entry(&bdma_chan->queue,
550 bdma_chan->active_tx = desc;
556 tsi721_start_dma(bdma_chan);
558 tsi721_dma_tx_err(bdma_chan, desc);
559 tsi_debug(DMA, &bdma_chan->dchan.dev->device,
561 bdma_chan->id, err);
565 tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d Exit",
566 bdma_chan->id);
571 struct tsi721_bdma_chan *bdma_chan = (struct tsi721_bdma_chan *)data;
574 dmac_int = ioread32(bdma_chan->regs + TSI721_DMAC_INT);
575 tsi_debug(DMA, &bdma_chan->dchan.dev->device, "DMAC%d_INT = 0x%x",
576 bdma_chan->id, dmac_int);
578 iowrite32(dmac_int, bdma_chan->regs + TSI721_DMAC_INT);
584 desc = bdma_chan->active_tx;
585 dmac_sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
586 tsi_err(&bdma_chan->dchan.dev->device,
588 bdma_chan->id, dmac_sts, desc->destid, desc->rio_addr);
595 tsi721_clr_stat(bdma_chan);
597 spin_lock(&bdma_chan->lock);
601 bdma_chan->regs + TSI721_DMAC_CTL);
604 dmac_sts = ioread32(bdma_chan->regs + TSI721_DMAC_STS);
609 tsi_err(&bdma_chan->dchan.dev->device,
610 "Failed to re-initiate DMAC%d", bdma_chan->id);
611 spin_unlock(&bdma_chan->lock);
616 iowrite32(((u64)bdma_chan->bd_phys >> 32),
617 bdma_chan->regs + TSI721_DMAC_DPTRH);
618 iowrite32(((u64)bdma_chan->bd_phys & TSI721_DMAC_DPTRL_MASK),
619 bdma_chan->regs + TSI721_DMAC_DPTRL);
622 iowrite32(((u64)bdma_chan->sts_phys >> 32),
623 bdma_chan->regs + TSI721_DMAC_DSBH);
624 iowrite32(((u64)bdma_chan->sts_phys & TSI721_DMAC_DSBL_MASK),
625 bdma_chan->regs + TSI721_DMAC_DSBL);
626 iowrite32(TSI721_DMAC_DSSZ_SIZE(bdma_chan->sts_size),
627 bdma_chan->regs + TSI721_DMAC_DSSZ);
631 bdma_chan->regs + TSI721_DMAC_INT);
633 ioread32(bdma_chan->regs + TSI721_DMAC_INT);
635 bdma_chan->wr_count = bdma_chan->wr_count_next = 0;
636 bdma_chan->sts_rdptr = 0;
639 desc = bdma_chan->active_tx;
642 list_add(&desc->desc_node, &bdma_chan->free_list);
643 bdma_chan->active_tx = NULL;
644 if (bdma_chan->active)
645 tsi721_advance_work(bdma_chan, NULL);
646 spin_unlock(&bdma_chan->lock);
650 tsi_err(&bdma_chan->dchan.dev->device,
652 bdma_chan->id);
658 tsi721_clr_stat(bdma_chan);
659 spin_lock(&bdma_chan->lock);
660 desc = bdma_chan->active_tx;
672 list_add(&desc->desc_node, &bdma_chan->free_list);
673 bdma_chan->active_tx = NULL;
674 if (bdma_chan->active)
675 tsi721_advance_work(bdma_chan, NULL);
676 spin_unlock(&bdma_chan->lock);
680 if (bdma_chan->active)
681 tsi721_advance_work(bdma_chan,
682 bdma_chan->active_tx);
683 spin_unlock(&bdma_chan->lock);
688 iowrite32(TSI721_DMAC_INT_ALL, bdma_chan->regs + TSI721_DMAC_INTE);
694 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(txd->chan);
699 tsi_err(&bdma_chan->dchan.dev->device,
701 bdma_chan->id, txd);
705 spin_lock_bh(&bdma_chan->lock);
707 if (!bdma_chan->active) {
708 spin_unlock_bh(&bdma_chan->lock);
714 list_add_tail(&desc->desc_node, &bdma_chan->queue);
715 tsi721_advance_work(bdma_chan, NULL);
717 spin_unlock_bh(&bdma_chan->lock);
723 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
727 tsi_debug(DMA, &dchan->dev->device, "DMAC%d", bdma_chan->id);
729 if (bdma_chan->bd_base)
733 if (tsi721_bdma_ch_init(bdma_chan, dma_desc_per_channel)) {
735 bdma_chan->id);
743 tsi721_bdma_ch_free(bdma_chan);
747 bdma_chan->tx_desc = desc;
753 list_add(&desc[i].desc_node, &bdma_chan->free_list);
758 bdma_chan->active = true;
759 tsi721_bdma_interrupt_enable(bdma_chan, 1);
764 static void tsi721_sync_dma_irq(struct tsi721_bdma_chan *bdma_chan)
766 struct tsi721_device *priv = to_tsi721(bdma_chan->dchan.device);
771 bdma_chan->id].vector);
773 bdma_chan->id].vector);
781 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
783 tsi_debug(DMA, &dchan->dev->device, "DMAC%d", bdma_chan->id);
785 if (!bdma_chan->bd_base)
788 tsi721_bdma_interrupt_enable(bdma_chan, 0);
789 bdma_chan->active = false;
790 tsi721_sync_dma_irq(bdma_chan);
791 tasklet_kill(&bdma_chan->tasklet);
792 INIT_LIST_HEAD(&bdma_chan->free_list);
793 kfree(bdma_chan->tx_desc);
794 tsi721_bdma_ch_free(bdma_chan);
801 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
804 spin_lock_bh(&bdma_chan->lock);
806 spin_unlock_bh(&bdma_chan->lock);
812 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
814 tsi_debug(DMA, &dchan->dev->device, "DMAC%d", bdma_chan->id);
816 spin_lock_bh(&bdma_chan->lock);
817 if (tsi721_dma_is_idle(bdma_chan) && bdma_chan->active) {
818 tsi721_advance_work(bdma_chan, NULL);
820 spin_unlock_bh(&bdma_chan->lock);
829 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
837 bdma_chan->id);
841 tsi_debug(DMA, &dchan->dev->device, "DMAC%d %s", bdma_chan->id,
862 bdma_chan->id);
866 spin_lock_bh(&bdma_chan->lock);
868 if (!list_empty(&bdma_chan->free_list)) {
869 desc = list_first_entry(&bdma_chan->free_list,
882 spin_unlock_bh(&bdma_chan->lock);
886 "DMAC%d free TXD is not available", bdma_chan->id);
895 struct tsi721_bdma_chan *bdma_chan = to_tsi721_chan(dchan);
899 tsi_debug(DMA, &dchan->dev->device, "DMAC%d", bdma_chan->id);
901 spin_lock_bh(&bdma_chan->lock);
903 bdma_chan->active = false;
905 while (!tsi721_dma_is_idle(bdma_chan)) {
911 bdma_chan->regs + TSI721_DMAC_CTL);
915 dmac_int = ioread32(bdma_chan->regs + TSI721_DMAC_INT);
920 if (bdma_chan->active_tx)
921 list_add(&bdma_chan->active_tx->desc_node, &list);
922 list_splice_init(&bdma_chan->queue, &list);
925 tsi721_dma_tx_err(bdma_chan, desc);
927 spin_unlock_bh(&bdma_chan->lock);
932 static void tsi721_dma_stop(struct tsi721_bdma_chan *bdma_chan)
934 if (!bdma_chan->active)
936 spin_lock_bh(&bdma_chan->lock);
937 if (!tsi721_dma_is_idle(bdma_chan)) {
942 bdma_chan->regs + TSI721_DMAC_CTL);
945 while (!tsi721_dma_is_idle(bdma_chan) && --timeout)
949 spin_unlock_bh(&bdma_chan->lock);
972 struct tsi721_bdma_chan *bdma_chan = &priv->bdma[i];
977 bdma_chan->regs = priv->regs + TSI721_DMAC_BASE(i);
979 bdma_chan->dchan.device = &mport->dma;
980 bdma_chan->dchan.cookie = 1;
981 bdma_chan->dchan.chan_id = i;
982 bdma_chan->id = i;
983 bdma_chan->active = false;
985 spin_lock_init(&bdma_chan->lock);
987 bdma_chan->active_tx = NULL;
988 INIT_LIST_HEAD(&bdma_chan->queue);
989 INIT_LIST_HEAD(&bdma_chan->free_list);
991 tasklet_init(&bdma_chan->tasklet, tsi721_dma_tasklet,
992 (unsigned long)bdma_chan);
993 list_add_tail(&bdma_chan->dchan.device_node,
1022 struct tsi721_bdma_chan *bdma_chan;
1029 bdma_chan = to_tsi721_chan(chan);
1030 if (bdma_chan->active) {
1031 tsi721_bdma_interrupt_enable(bdma_chan, 0);
1032 bdma_chan->active = false;
1033 tsi721_sync_dma_irq(bdma_chan);
1034 tasklet_kill(&bdma_chan->tasklet);
1035 INIT_LIST_HEAD(&bdma_chan->free_list);
1036 kfree(bdma_chan->tx_desc);
1037 tsi721_bdma_ch_free(bdma_chan);