Lines Matching refs:iowrite32
89 iowrite32(data, priv->regs + offset);
142 iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT);
171 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
172 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
174 iowrite32(0, regs + TSI721_DMAC_DWRCNT);
191 iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP);
282 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
324 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
327 iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);
373 iowrite32(regval,
435 iowrite32(rd_ptr & (IDB_QSIZE - 1),
441 iowrite32(regval,
467 iowrite32(0, priv->regs + TSI721_DEV_INTE);
488 iowrite32(intval,
505 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
521 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
563 iowrite32(dev_int, priv->regs + TSI721_DEV_INTE);
574 iowrite32(TSI721_SR_CHINT_ALL,
576 iowrite32(TSI721_SR_CHINT_IDBQRCV,
580 iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
591 iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE);
599 iowrite32(intr, priv->regs + TSI721_DEV_INTE);
678 iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
980 iowrite32(rval, priv->regs + TSI721_LUT_DATA0);
982 iowrite32(rval, priv->regs + TSI721_LUT_DATA1);
984 iowrite32(rval, priv->regs + TSI721_LUT_DATA2);
987 iowrite32(rval, priv->regs + TSI721_ZONE_SEL);
992 iowrite32(TSI721_OBWIN_SIZE(size) << 8,
994 iowrite32((u32)(ob_win->base >> 32), priv->regs + TSI721_OBWINUB(obw));
995 iowrite32((u32)(ob_win->base & TSI721_OBWINLB_BA) | TSI721_OBWINLB_WEN,
1019 iowrite32(0, priv->regs + TSI721_OBWINLB(i));
1041 iowrite32(0, priv->regs + TSI721_OBWINLB(i));
1044 iowrite32(0, priv->regs + TSI721_LUT_DATA0);
1045 iowrite32(0, priv->regs + TSI721_LUT_DATA1);
1046 iowrite32(0, priv->regs + TSI721_LUT_DATA2);
1055 iowrite32(rval, priv->regs + TSI721_ZONE_SEL);
1211 iowrite32(TSI721_IBWIN_SIZE(ibw_size) << 8,
1214 iowrite32(((u64)loc_start >> 32), priv->regs + TSI721_IBWIN_TUA(i));
1215 iowrite32(((u64)loc_start & TSI721_IBWIN_TLA_ADD),
1218 iowrite32(ibw_start >> 32, priv->regs + TSI721_IBWIN_UB(i));
1219 iowrite32((ibw_start & TSI721_IBWIN_LB_BA) | TSI721_IBWIN_LB_WEN,
1283 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1308 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1326 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1351 iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL);
1382 iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE),
1384 iowrite32(((u64)priv->idb_dma >> 32),
1386 iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR),
1389 iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));
1391 iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));
1393 iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
1481 iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH);
1482 iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
1486 iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH);
1487 iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
1489 iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
1493 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
1498 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1520 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1547 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1551 iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));
1562 iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),
1577 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1582 iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));
1594 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1608 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1612 iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));
1623 iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),
1638 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1643 iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));
1655 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1718 iowrite32(priv->omsg_ring[mbox].wr_count,
1779 iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch));
1829 iowrite32(TSI721_OBDMAC_INT_ERROR,
1831 iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT,
1841 iowrite32(priv->omsg_ring[ch].tx_slot,
1849 iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch));
1857 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1945 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32),
1947 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys &
1952 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32),
1954 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys &
1957 iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size),
2006 iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT,
2133 iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch));
2147 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
2248 iowrite32((u32)priv->mport.host_deviceid,
2258 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32),
2260 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys &
2263 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2267 iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32),
2269 iowrite32(((u32)priv->imsg_ring[mbox].imd_phys &
2272 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2310 iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch));
2314 iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch));
2489 iowrite32(priv->imsg_ring[mbox].desc_rdptr,
2499 iowrite32(priv->imsg_ring[mbox].fq_wrptr,
2515 iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG);
2516 iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT);
2517 iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT);
2520 iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO);
2525 iowrite32(TSI721_IBDMAC_INT_MASK,
2528 iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch));
2530 iowrite32(TSI721_SMSG_ECC_COR_LOG_MASK,
2532 iowrite32(TSI721_SMSG_ECC_NCOR_MASK,
2581 iowrite32(0, priv->regs + TSI721_DEV_INTE);
2584 iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE);
2588 iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch));
2592 iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch));
2595 iowrite32(0, priv->regs + TSI721_SMSG_INTE);
2599 iowrite32(0,
2603 iowrite32(0, priv->regs + TSI721_BDMA_INTE);
2607 iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch));
2610 iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE);
2613 iowrite32(0, priv->regs + TSI721_PC2SR_INTE);
2616 iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE);
2619 iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE);
2620 iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN);
2710 iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
2715 iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
2719 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));