Lines Matching defs:rval
314 u32 rval;
316 rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE);
319 rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX;
321 rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX;
327 iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);
927 u32 rval;
978 rval = (u32)(rio_addr & TSI721_LUT_DATA0_ADD) |
980 iowrite32(rval, priv->regs + TSI721_LUT_DATA0);
981 rval = (u32)(rio_addr >> 32);
982 iowrite32(rval, priv->regs + TSI721_LUT_DATA1);
983 rval = destid;
984 iowrite32(rval, priv->regs + TSI721_LUT_DATA2);
986 rval = TSI721_ZONE_SEL_GO | (obw << 3) | i;
987 iowrite32(rval, priv->regs + TSI721_ZONE_SEL);
1037 u32 rval;
1054 rval = TSI721_ZONE_SEL_GO | (i << 3) | z;
1055 iowrite32(rval, priv->regs + TSI721_ZONE_SEL);
1541 u32 rval;
1550 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1551 iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));
1561 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1562 iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),
1571 u32 rval;
1580 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1581 rval &= ~inte_mask;
1582 iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));
1592 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1593 rval &= ~TSI721_INT_IMSG_CHAN(ch);
1594 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1602 u32 rval;
1611 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1612 iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));
1622 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1623 iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),
1632 u32 rval;
1641 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1642 rval &= ~inte_mask;
1643 iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));
1653 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1654 rval &= ~TSI721_INT_OMSG_CHAN(ch);
1655 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
2550 u32 rval;
2552 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_ERR_STS_CSR(0, 0));
2553 if (rval & RIO_PORT_N_ERR_STS_PORT_OK) {
2554 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL2_CSR(0, 0));
2555 attr->link_speed = (rval & RIO_PORT_N_CTL2_SEL_BAUD) >> 28;
2556 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL_CSR(0, 0));
2557 attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27;