Lines Matching defs:zpc
41 static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm,
44 return readl(zpc->base + (hwpwm + 1) * 0x10 + offset);
47 static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm,
50 writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset);
53 static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm,
58 data = zx_pwm_readl(zpc, hwpwm, offset);
61 zx_pwm_writel(zpc, hwpwm, offset, data);
67 struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
73 value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE);
86 rate = clk_get_rate(zpc->wclk);
88 tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD);
92 tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY);
100 struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
107 rate = clk_get_rate(zpc->wclk);
134 zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_EN, 0);
137 zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_CLKDIV_MASK,
139 zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles);
140 zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles);
144 zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
153 struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
160 zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_POLAR,
174 ret = clk_prepare_enable(zpc->wclk);
178 zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
181 zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
183 clk_disable_unprepare(zpc->wclk);
198 struct zx_pwm_chip *zpc;
203 zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL);
204 if (!zpc)
208 zpc->base = devm_ioremap_resource(&pdev->dev, res);
209 if (IS_ERR(zpc->base))
210 return PTR_ERR(zpc->base);
212 zpc->pclk = devm_clk_get(&pdev->dev, "pclk");
213 if (IS_ERR(zpc->pclk))
214 return PTR_ERR(zpc->pclk);
216 zpc->wclk = devm_clk_get(&pdev->dev, "wclk");
217 if (IS_ERR(zpc->wclk))
218 return PTR_ERR(zpc->wclk);
220 ret = clk_prepare_enable(zpc->pclk);
224 zpc->chip.dev = &pdev->dev;
225 zpc->chip.ops = &zx_pwm_ops;
226 zpc->chip.base = -1;
227 zpc->chip.npwm = 4;
228 zpc->chip.of_xlate = of_pwm_xlate_with_flags;
229 zpc->chip.of_pwm_n_cells = 3;
235 for (i = 0; i < zpc->chip.npwm; i++)
236 zx_pwm_set_mask(zpc, i, ZX_PWM_MODE, ZX_PWM_EN, 0);
238 ret = pwmchip_add(&zpc->chip);
241 clk_disable_unprepare(zpc->pclk);
245 platform_set_drvdata(pdev, zpc);
252 struct zx_pwm_chip *zpc = platform_get_drvdata(pdev);
255 ret = pwmchip_remove(&zpc->chip);
256 clk_disable_unprepare(zpc->pclk);