Lines Matching refs:vt8500
3 * drivers/pwm/pwm-vt8500.c
59 static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
64 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
68 dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
75 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
81 err = clk_enable(vt8500->clk);
87 c = clk_get_rate(vt8500->clk);
100 clk_disable(vt8500->clk);
108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
109 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
112 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
115 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
120 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
122 clk_disable(vt8500->clk);
128 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
132 err = clk_enable(vt8500->clk);
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
140 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
141 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
148 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
151 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
153 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
154 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
156 clk_disable(vt8500->clk);
163 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
166 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
173 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
174 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
188 { .compatible = "via,vt8500-pwm", },
261 .name = "vt8500-pwm",