Lines Matching refs:rate
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
100 unsigned long rate, required_clk_rate;
122 * cycles at the PWM clock rate will take period_ns nanoseconds.
130 * nums_channels == 1 then only the clock rate can be modified
136 * with the maximum possible rate that the controller can
140 * required_clk_rate is a reference rate for source clock and
142 * source clock rate as required_clk_rate, PWM controller will
152 /* Store the new rate for further references */
156 rate = pc->clk_rate >> PWM_DUTY_WIDTH;
158 /* Consider precision in PWM_SCALE_WIDTH rate calculation */
160 rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
167 if (rate > 0)
168 rate--;
171 * Make sure that the rate will fit in the register's frequency
174 if (rate >> PWM_SCALE_WIDTH)
177 val |= rate << PWM_SCALE_SHIFT;