Lines Matching refs:pwm
3 * drivers/pwm/pwm-tegra.c
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
45 #include <linux/pwm.h>
95 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
183 if (!pwm_is_enabled(pwm)) {
190 pwm_writel(pc, pwm->hwpwm, val);
195 if (!pwm_is_enabled(pwm))
201 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
211 val = pwm_readl(pc, pwm->hwpwm);
213 pwm_writel(pc, pwm->hwpwm, val);
218 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
223 val = pwm_readl(pc, pwm->hwpwm);
225 pwm_writel(pc, pwm->hwpwm, val);
239 struct tegra_pwm_chip *pwm;
243 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
244 if (!pwm)
247 pwm->soc = of_device_get_match_data(&pdev->dev);
248 pwm->dev = &pdev->dev;
251 pwm->regs = devm_ioremap_resource(&pdev->dev, r);
252 if (IS_ERR(pwm->regs))
253 return PTR_ERR(pwm->regs);
255 platform_set_drvdata(pdev, pwm);
257 pwm->clk = devm_clk_get(&pdev->dev, NULL);
258 if (IS_ERR(pwm->clk))
259 return PTR_ERR(pwm->clk);
262 ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
273 pwm->clk_rate = clk_get_rate(pwm->clk);
276 pwm->min_period_ns =
277 (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
279 pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
280 if (IS_ERR(pwm->rst)) {
281 ret = PTR_ERR(pwm->rst);
286 reset_control_deassert(pwm->rst);
288 pwm->chip.dev = &pdev->dev;
289 pwm->chip.ops = &tegra_pwm_ops;
290 pwm->chip.base = -1;
291 pwm->chip.npwm = pwm->soc->num_channels;
293 ret = pwmchip_add(&pwm->chip);
296 reset_control_assert(pwm->rst);
349 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
350 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
351 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
362 .name = "tegra-pwm",
375 MODULE_ALIAS("platform:tegra-pwm");