Lines Matching defs:sun4i_pwm
116 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
121 clk_rate = clk_get_rate(sun4i_pwm->clk);
123 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
131 sun4i_pwm->data->has_direct_mod_clk_output) {
140 sun4i_pwm->data->has_prescaler_bypass)
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
168 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
176 clk_rate = clk_get_rate(sun4i_pwm->clk);
178 *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
188 if (sun4i_pwm->data->has_prescaler_bypass) {
234 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
245 ret = clk_prepare_enable(sun4i_pwm->clk);
252 ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
257 clk_disable_unprepare(sun4i_pwm->clk);
261 spin_lock(&sun4i_pwm->ctrl_lock);
262 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
264 if (sun4i_pwm->data->has_direct_mod_clk_output) {
268 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
269 spin_unlock(&sun4i_pwm->ctrl_lock);
279 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
286 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
287 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
300 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
302 spin_unlock(&sun4i_pwm->ctrl_lock);
309 if (time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
310 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
318 spin_lock(&sun4i_pwm->ctrl_lock);
319 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
322 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
323 spin_unlock(&sun4i_pwm->ctrl_lock);
325 clk_disable_unprepare(sun4i_pwm->clk);