Lines Matching refs:spc
53 static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
57 return readl_relaxed(spc->base + offset);
60 static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
65 writel_relaxed(val, spc->base + offset);
71 struct sprd_pwm_chip *spc =
73 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
84 dev_err(spc->dev, "failed to enable pwm%u clocks\n",
89 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
103 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
108 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
119 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
122 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
152 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
153 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
154 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
162 struct sprd_pwm_chip *spc =
164 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
177 dev_err(spc->dev,
184 ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
189 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
196 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
210 static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
216 struct sprd_pwm_chn *chn = &spc->chn[i];
223 ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,
229 return dev_err_probe(spc->dev, ret,
238 dev_err(spc->dev, "no available PWM channels\n");
242 spc->num_pwms = i;
249 struct sprd_pwm_chip *spc;
252 spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
253 if (!spc)
256 spc->base = devm_platform_ioremap_resource(pdev, 0);
257 if (IS_ERR(spc->base))
258 return PTR_ERR(spc->base);
260 spc->dev = &pdev->dev;
261 platform_set_drvdata(pdev, spc);
263 ret = sprd_pwm_clk_init(spc);
267 spc->chip.dev = &pdev->dev;
268 spc->chip.ops = &sprd_pwm_ops;
269 spc->chip.base = -1;
270 spc->chip.npwm = spc->num_pwms;
272 ret = pwmchip_add(&spc->chip);
281 struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
283 return pwmchip_remove(&spc->chip);