Lines Matching refs:prescaler
10 * With the prescaler setting you can select which bit of the counter is used
16 * | prescaler | reset | counter bits | frequency | period length |
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
28 * - The counter is not reset if you switch the prescaler which leads
54 #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler) (1 << (7 - (prescaler)))
55 #define SL28CPLD_PWM_PERIOD(prescaler) \
56 (NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))
63 * max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
64 * max_duty_cycle = 1 << (7 - prescaler)
96 int prescaler;
102 prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
103 state->period = SL28CPLD_PWM_PERIOD(prescaler);
110 * Sanitize values for the PWM core. Depending on the prescaler it
124 unsigned int cycle, prescaler;
134 * Calculate the prescaler. Pick the biggest period that isn't
137 prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
138 prescaler = order_base_2(prescaler);
140 if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
143 ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
148 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));
152 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
155 * We don't need to check the actual prescaler setting, because only
156 * if the prescaler is 0 we can have this particular value.
165 * To avoid glitches when we switch the prescaler, we have to make sure
168 * Take the current prescaler (or the current period length) into
170 * prescaler first. If the period length is decreasing we have to