Lines Matching refs:pc
64 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
65 u32 enable_conf = pc->data->enable_conf;
71 ret = clk_enable(pc->pclk);
75 clk_rate = clk_get_rate(pc->clk);
77 tmp = readl_relaxed(pc->base + pc->data->regs.period);
78 tmp *= pc->data->prescaler * NSEC_PER_SEC;
81 tmp = readl_relaxed(pc->base + pc->data->regs.duty);
82 tmp *= pc->data->prescaler * NSEC_PER_SEC;
85 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
88 if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
93 clk_disable(pc->pclk);
99 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
104 clk_rate = clk_get_rate(pc->clk);
113 pc->data->prescaler * NSEC_PER_SEC);
116 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
122 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
123 if (pc->data->supports_lock) {
125 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
128 writel(period, pc->base + pc->data->regs.period);
129 writel(duty, pc->base + pc->data->regs.duty);
131 if (pc->data->supports_polarity) {
144 if (pc->data->supports_lock)
147 writel(ctrl, pc->base + pc->data->regs.ctrl);
154 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
155 u32 enable_conf = pc->data->enable_conf;
160 ret = clk_enable(pc->clk);
165 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
172 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
175 clk_disable(pc->clk);
183 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
188 ret = clk_enable(pc->pclk);
196 !pc->data->supports_lock) {
211 clk_disable(pc->pclk);
289 struct rockchip_pwm_chip *pc;
299 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
300 if (!pc)
304 pc->base = devm_ioremap_resource(&pdev->dev, r);
305 if (IS_ERR(pc->base))
306 return PTR_ERR(pc->base);
308 pc->clk = devm_clk_get(&pdev->dev, "pwm");
309 if (IS_ERR(pc->clk)) {
310 pc->clk = devm_clk_get(&pdev->dev, NULL);
311 if (IS_ERR(pc->clk))
312 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
319 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
321 pc->pclk = pc->clk;
323 if (IS_ERR(pc->pclk)) {
324 ret = PTR_ERR(pc->pclk);
330 ret = clk_prepare_enable(pc->clk);
336 ret = clk_prepare_enable(pc->pclk);
342 platform_set_drvdata(pdev, pc);
344 pc->data = id->data;
345 pc->chip.dev = &pdev->dev;
346 pc->chip.ops = &rockchip_pwm_ops;
347 pc->chip.base = -1;
348 pc->chip.npwm = 1;
350 if (pc->data->supports_polarity) {
351 pc->chip.of_xlate = of_pwm_xlate_with_flags;
352 pc->chip.of_pwm_n_cells = 3;
355 enable_conf = pc->data->enable_conf;
356 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
359 ret = pwmchip_add(&pc->chip);
367 clk_disable(pc->clk);
369 clk_disable(pc->pclk);
374 clk_disable_unprepare(pc->pclk);
376 clk_disable_unprepare(pc->clk);
383 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
385 clk_unprepare(pc->pclk);
386 clk_unprepare(pc->clk);
388 return pwmchip_remove(&pc->chip);