Lines Matching defs:period
42 unsigned long period;
77 tmp = readl_relaxed(pc->base + pc->data->regs.period);
79 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
100 unsigned long period, duty;
107 * Since period and duty cycle registers have a width of 32
108 * bits, every possible input period can be obtained using the
111 div = clk_rate * state->period;
112 period = DIV_ROUND_CLOSEST_ULL(div,
119 * Lock the period and duty of previous configuration, then
120 * change the duty and period, that would not be effective.
128 writel(period, pc->base + pc->data->regs.period);
141 * the configuration of duty, period and polarity
142 * would be effective together at next period.
225 .period = 0x08,
238 .period = 0x04,
252 .period = 0x04,
266 .period = 0x04,