Lines Matching defs:tpu
72 struct tpu_device *tpu;
94 void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET
105 dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n",
132 spin_lock_irqsave(&pwm->tpu->lock, flags);
133 value = ioread16(pwm->tpu->base + TPU_TSTR);
140 iowrite16(value, pwm->tpu->base + TPU_TSTR);
141 spin_unlock_irqrestore(&pwm->tpu->lock, flags);
150 pm_runtime_get_sync(&pwm->tpu->pdev->dev);
151 ret = clk_prepare_enable(pwm->tpu->clk);
153 dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n");
182 dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
200 clk_disable_unprepare(pwm->tpu->clk);
201 pm_runtime_put(&pwm->tpu->pdev->dev);
212 struct tpu_device *tpu = to_tpu_device(chip);
222 pwm->tpu = tpu;
249 struct tpu_device *tpu = to_tpu_device(chip);
261 clk_rate = clk_get_rate(tpu->clk);
271 dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
284 dev_dbg(&tpu->pdev->dev,
306 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel,
385 struct tpu_device *tpu;
389 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
390 if (tpu == NULL)
393 spin_lock_init(&tpu->lock);
394 tpu->pdev = pdev;
398 tpu->base = devm_ioremap_resource(&pdev->dev, res);
399 if (IS_ERR(tpu->base))
400 return PTR_ERR(tpu->base);
402 tpu->clk = devm_clk_get(&pdev->dev, NULL);
403 if (IS_ERR(tpu->clk)) {
405 return PTR_ERR(tpu->clk);
409 platform_set_drvdata(pdev, tpu);
411 tpu->chip.dev = &pdev->dev;
412 tpu->chip.ops = &tpu_pwm_ops;
413 tpu->chip.of_xlate = of_pwm_xlate_with_flags;
414 tpu->chip.of_pwm_n_cells = 3;
415 tpu->chip.base = -1;
416 tpu->chip.npwm = TPU_CHANNEL_MAX;
420 ret = pwmchip_add(&tpu->chip);
432 struct tpu_device *tpu = platform_get_drvdata(pdev);
435 ret = pwmchip_remove(&tpu->chip);
444 { .compatible = "renesas,tpu-r8a73a4", },
445 { .compatible = "renesas,tpu-r8a7740", },
446 { .compatible = "renesas,tpu-r8a7790", },
447 { .compatible = "renesas,tpu", },
458 .name = "renesas-tpu-pwm",
468 MODULE_ALIAS("platform:renesas-tpu-pwm");