Lines Matching refs:rp
51 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
54 writel(data, rp->base + offset);
57 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
59 return readl(rp->base + offset);
62 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
67 value = rcar_pwm_read(rp, offset);
70 rcar_pwm_write(rp, value, offset);
73 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
75 unsigned long clk_rate = clk_get_rate(rp->clk);
89 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
94 value = rcar_pwm_read(rp, RCAR_PWMCR);
103 rcar_pwm_write(rp, value, RCAR_PWMCR);
106 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
110 unsigned long clk_rate = clk_get_rate(rp->clk);
128 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
143 static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
148 value = rcar_pwm_read(rp, RCAR_PWMCNT);
153 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
158 static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
160 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
166 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
174 rcar_pwm_disable(rp);
178 div = rcar_pwm_get_clock_division(rp, state->period);
182 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
184 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
186 rcar_pwm_set_clock_control(rp, div);
189 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
192 ret = rcar_pwm_enable(rp);