Lines Matching refs:value
237 u32 value;
243 value = readl(meson->base + REG_MISC_AB);
244 value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
245 value |= channel->pre_div << channel_data->clk_div_shift;
246 value |= channel_data->clk_en_mask;
247 writel(value, meson->base + REG_MISC_AB);
249 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
251 writel(value, meson->base + channel_data->reg_offset);
253 value = readl(meson->base + REG_MISC_AB);
254 value |= channel_data->pwm_en_mask;
255 writel(value, meson->base + REG_MISC_AB);
263 u32 value;
267 value = readl(meson->base + REG_MISC_AB);
268 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
269 writel(value, meson->base + REG_MISC_AB);
343 u32 value, tmp;
351 value = readl(meson->base + REG_MISC_AB);
354 state->enabled = (value & tmp) == tmp;
356 tmp = value >> channel_data->clk_div_shift;
359 value = readl(meson->base + channel_data->reg_offset);
361 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
362 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);