Lines Matching defs:lpc18xx_pwm
112 static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm,
115 writel(val, lpc18xx_pwm->base + reg);
118 static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm,
121 return readl(lpc18xx_pwm->base + reg);
124 static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
130 mutex_lock(&lpc18xx_pwm->res_lock);
137 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE);
140 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val);
142 mutex_unlock(&lpc18xx_pwm->res_lock);
147 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
150 val = (u64)period_ns * lpc18xx_pwm->clk_rate;
153 lpc18xx_pwm_writel(lpc18xx_pwm,
154 LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
157 lpc18xx_pwm_writel(lpc18xx_pwm,
158 LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
165 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
169 val = (u64)duty_ns * lpc18xx_pwm->clk_rate;
172 lpc18xx_pwm_writel(lpc18xx_pwm,
176 lpc18xx_pwm_writel(lpc18xx_pwm,
184 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
187 if (period_ns < lpc18xx_pwm->min_period_ns ||
188 period_ns > lpc18xx_pwm->max_period_ns) {
193 mutex_lock(&lpc18xx_pwm->period_lock);
195 requested_events = bitmap_weight(&lpc18xx_pwm->event_map,
203 if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns &&
204 lpc18xx_pwm->period_ns) {
207 mutex_unlock(&lpc18xx_pwm->period_lock);
211 if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) ||
212 !lpc18xx_pwm->period_ns) {
213 lpc18xx_pwm->period_ns = period_ns;
219 mutex_unlock(&lpc18xx_pwm->period_lock);
235 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
240 lpc18xx_pwm_writel(lpc18xx_pwm,
245 lpc18xx_pwm_writel(lpc18xx_pwm,
250 set_event = lpc18xx_pwm->period_event;
255 clear_event = lpc18xx_pwm->period_event;
259 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm),
261 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
263 lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action);
270 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
273 lpc18xx_pwm_writel(lpc18xx_pwm,
275 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0);
276 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0);
281 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
285 event = find_first_zero_bit(&lpc18xx_pwm->event_map,
289 dev_err(lpc18xx_pwm->dev,
294 set_bit(event, &lpc18xx_pwm->event_map);
302 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
305 clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map);
326 struct lpc18xx_pwm_chip *lpc18xx_pwm;
331 lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm),
333 if (!lpc18xx_pwm)
336 lpc18xx_pwm->dev = &pdev->dev;
338 lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
339 if (IS_ERR(lpc18xx_pwm->base))
340 return PTR_ERR(lpc18xx_pwm->base);
342 lpc18xx_pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
343 if (IS_ERR(lpc18xx_pwm->pwm_clk)) {
345 return PTR_ERR(lpc18xx_pwm->pwm_clk);
348 ret = clk_prepare_enable(lpc18xx_pwm->pwm_clk);
354 lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
355 if (!lpc18xx_pwm->clk_rate) {
361 mutex_init(&lpc18xx_pwm->res_lock);
362 mutex_init(&lpc18xx_pwm->period_lock);
365 do_div(val, lpc18xx_pwm->clk_rate);
366 lpc18xx_pwm->max_period_ns = val;
368 lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC,
369 lpc18xx_pwm->clk_rate);
371 lpc18xx_pwm->chip.dev = &pdev->dev;
372 lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops;
373 lpc18xx_pwm->chip.base = -1;
374 lpc18xx_pwm->chip.npwm = 16;
375 lpc18xx_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
376 lpc18xx_pwm->chip.of_pwm_n_cells = 3;
379 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG,
386 set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map);
387 lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD;
389 lpc18xx_pwm_writel(lpc18xx_pwm,
390 LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event),
393 val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) |
395 lpc18xx_pwm_writel(lpc18xx_pwm,
396 LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val);
398 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT,
399 BIT(lpc18xx_pwm->period_event));
401 for (i = 0; i < lpc18xx_pwm->chip.npwm; i++) {
404 pwm = &lpc18xx_pwm->chip.pwms[i];
406 data = devm_kzalloc(lpc18xx_pwm->dev, sizeof(*data),
416 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
421 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val);
423 ret = pwmchip_add(&lpc18xx_pwm->chip);
429 platform_set_drvdata(pdev, lpc18xx_pwm);
434 clk_disable_unprepare(lpc18xx_pwm->pwm_clk);
440 struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev);
443 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
444 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL,
447 clk_disable_unprepare(lpc18xx_pwm->pwm_clk);
449 return pwmchip_remove(&lpc18xx_pwm->chip);