Lines Matching refs:val
72 u32 val;
127 p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
140 u32 rate, val, prescale;
148 val = readl(tpm->base + PWM_IMX_TPM_SC);
149 prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
155 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
156 if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
166 state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
178 u32 val, cmod, cur_prescale;
192 val = readl(tpm->base + PWM_IMX_TPM_SC);
193 cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
194 cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
199 val &= ~PWM_IMX_TPM_SC_PS;
200 val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
201 writel(val, tpm->base + PWM_IMX_TPM_SC);
231 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
241 != p->val) {
254 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
255 val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
265 val |= PWM_IMX_TPM_CnSC_MSB;
266 val |= (state->polarity == PWM_POLARITY_NORMAL) ?
270 writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
274 val = readl(tpm->base + PWM_IMX_TPM_SC);
277 val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
280 val &= ~PWM_IMX_TPM_SC_CMOD;
282 writel(val, tpm->base + PWM_IMX_TPM_SC);
340 u32 val;
375 val = readl(tpm->base + PWM_IMX_TPM_PARAM);
376 tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);