Lines Matching refs:val
81 u32 reg, u32 val)
83 writel(val, chip->base + reg);
95 u32 val, div, duty, timebase;
137 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
138 val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
139 val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
141 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
143 val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
145 img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
155 u32 val;
163 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
164 val |= BIT(pwm->hwpwm);
165 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
176 u32 val;
179 val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
180 val &= ~BIT(pwm->hwpwm);
181 img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
241 u64 val;
299 val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
300 do_div(val, clk_rate);
301 pwm->max_period_ns = val;
303 val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
304 do_div(val, clk_rate);
305 pwm->min_period_ns = val;