Lines Matching defs:fpc
62 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
66 regmap_read(fpc->regmap, FTM_FMS, &val);
68 regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
72 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
74 regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
92 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
94 ret = clk_prepare_enable(fpc->ipg_clk);
95 if (!ret && fpc->soc->has_enable_bits) {
96 mutex_lock(&fpc->lock);
97 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
99 mutex_unlock(&fpc->lock);
107 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
109 if (fpc->soc->has_enable_bits) {
110 mutex_lock(&fpc->lock);
111 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
113 mutex_unlock(&fpc->lock);
116 clk_disable_unprepare(fpc->ipg_clk);
119 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
125 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
128 do_div(exval, rate >> fpc->period.clk_ps);
132 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
141 c = clk_get_rate(fpc->clk[index]);
159 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
167 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
172 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
173 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
183 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
187 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
190 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
195 unsigned int period = fpc->period.mod_period + 1;
196 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
204 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
209 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
216 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
221 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
228 static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
238 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
239 dev_err(fpc->chip.dev, "failed to calculate new period\n");
243 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
251 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
252 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
253 dev_err(fpc->chip.dev,
258 if (fpc->period.clk_select != periodcfg.clk_select) {
260 enum fsl_pwm_clk oldclk = fpc->period.clk_select;
263 ret = clk_prepare_enable(fpc->clk[newclk]);
266 clk_disable_unprepare(fpc->clk[oldclk]);
271 ftm_clear_write_protection(fpc);
274 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
276 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
278 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
280 fpc->period = periodcfg;
283 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
285 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
287 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
293 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
295 ftm_set_write_protection(fpc);
303 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
316 mutex_lock(&fpc->lock);
320 regmap_update_bits(fpc->regmap, FTM_OUTMASK,
322 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
323 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
329 ret = fsl_pwm_apply_config(fpc, pwm, newstate);
335 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
339 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
341 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
345 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
350 mutex_unlock(&fpc->lock);
361 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
365 ret = clk_prepare_enable(fpc->ipg_clk);
369 regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
370 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
371 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
373 clk_disable_unprepare(fpc->ipg_clk);
401 struct fsl_pwm_chip *fpc;
406 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
407 if (!fpc)
410 mutex_init(&fpc->lock);
412 fpc->soc = of_device_get_match_data(&pdev->dev);
413 fpc->chip.dev = &pdev->dev;
420 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
422 if (IS_ERR(fpc->regmap)) {
424 return PTR_ERR(fpc->regmap);
427 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
428 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
430 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
433 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
434 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
435 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
437 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
438 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
439 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
441 fpc->clk[FSL_PWM_CLK_CNTEN] =
442 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
443 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
444 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
450 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
451 if (IS_ERR(fpc->ipg_clk))
452 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
455 fpc->chip.ops = &fsl_pwm_ops;
456 fpc->chip.of_xlate = of_pwm_xlate_with_flags;
457 fpc->chip.of_pwm_n_cells = 3;
458 fpc->chip.base = -1;
459 fpc->chip.npwm = 8;
461 ret = pwmchip_add(&fpc->chip);
467 platform_set_drvdata(pdev, fpc);
469 return fsl_pwm_init(fpc);
474 struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
476 return pwmchip_remove(&fpc->chip);
482 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
485 regcache_cache_only(fpc->regmap, true);
486 regcache_mark_dirty(fpc->regmap);
488 for (i = 0; i < fpc->chip.npwm; i++) {
489 struct pwm_device *pwm = &fpc->chip.pwms[i];
494 clk_disable_unprepare(fpc->ipg_clk);
499 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
500 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
508 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
511 for (i = 0; i < fpc->chip.npwm; i++) {
512 struct pwm_device *pwm = &fpc->chip.pwms[i];
517 clk_prepare_enable(fpc->ipg_clk);
522 clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
523 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
527 regcache_cache_only(fpc->regmap, false);
528 regcache_sync(fpc->regmap);