Lines Matching refs:channel
159 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
162 struct idt82p33 *idt82p33 = channel->idt82p33;
166 if (channel->pll_mode == mode)
169 err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
178 err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
183 channel->pll_mode = dpll_mode;
188 static int _idt82p33_gettime(struct idt82p33_channel *channel,
191 struct idt82p33 *idt82p33 = channel->idt82p33;
200 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
209 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
225 static int _idt82p33_settime(struct idt82p33_channel *channel,
228 struct idt82p33 *idt82p33 = channel->idt82p33;
239 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
260 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
269 static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
271 struct idt82p33 *idt82p33 = channel->idt82p33;
278 err = _idt82p33_gettime(channel, &ts);
288 err = _idt82p33_settime(channel, &ts);
293 static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
295 struct idt82p33 *idt82p33 = channel->idt82p33;
301 if (scaled_ppm == channel->current_freq_ppb)
333 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
338 err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
342 channel->current_freq_ppb = scaled_ppm;
348 struct idt82p33_channel *channel, s64 *overhead_ns)
350 struct idt82p33 *idt82p33 = channel->idt82p33;
366 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
383 struct idt82p33_channel *channel)
385 struct idt82p33 *idt82p33 = channel->idt82p33;
402 channel->dpll_tod_cnfg + i,
420 struct idt82p33_channel *channel, s64 *overhead_ns)
428 err = _idt82p33_settime(channel, &ts1);
433 err = _idt82p33_gettime(channel, &ts2);
441 static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
444 struct idt82p33 *idt82p33 = channel->idt82p33;
449 err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
454 err = idt82p33_measure_one_byte_write_overhead(channel,
460 err = idt82p33_measure_tod_write_9_byte_overhead(channel);
489 idt82p33->channel[0].output_mask = val;
492 idt82p33->channel[1].output_mask = val;
511 i, idt82p33->channel[i].output_mask);
515 static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
517 struct idt82p33 *idt82p33 = channel->idt82p33;
521 if (enable == channel->sync_tod_on) {
523 mod_delayed_work(system_wq, &channel->sync_tod_work,
529 err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
539 err = idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
544 channel->sync_tod_on = enable;
547 mod_delayed_work(system_wq, &channel->sync_tod_work,
556 struct idt82p33_channel *channel =
558 struct idt82p33 *idt82p33 = channel->idt82p33;
562 (void)idt82p33_sync_tod(channel, false);
567 static int idt82p33_pps_enable(struct idt82p33_channel *channel, bool enable)
569 struct idt82p33 *idt82p33 = channel->idt82p33;
573 mask = channel->output_mask;
601 static int idt82p33_enable_tod(struct idt82p33_channel *channel)
603 struct idt82p33 *idt82p33 = channel->idt82p33;
609 err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg,
614 err = idt82p33_pps_enable(channel, false);
619 err = idt82p33_measure_tod_write_overhead(channel);
624 err = _idt82p33_settime(channel, &ts);
629 return idt82p33_sync_tod(channel, true);
634 struct idt82p33_channel *channel;
639 channel = &idt82p33->channel[i];
641 if (channel->ptp_clock) {
642 ptp_clock_unregister(channel->ptp_clock);
643 cancel_delayed_work_sync(&channel->sync_tod_work);
651 struct idt82p33_channel *channel =
653 struct idt82p33 *idt82p33 = channel->idt82p33;
662 err = idt82p33_pps_enable(channel, false);
669 err = idt82p33_pps_enable(channel, true);
679 struct idt82p33_channel *channel =
681 struct idt82p33 *idt82p33 = channel->idt82p33;
685 err = _idt82p33_adjfine(channel, scaled_ppm);
693 struct idt82p33_channel *channel =
695 struct idt82p33 *idt82p33 = channel->idt82p33;
705 err = _idt82p33_adjtime(channel, delta_ns);
712 err = idt82p33_sync_tod(channel, true);
721 struct idt82p33_channel *channel =
723 struct idt82p33 *idt82p33 = channel->idt82p33;
727 err = _idt82p33_gettime(channel, ts);
736 struct idt82p33_channel *channel =
738 struct idt82p33 *idt82p33 = channel->idt82p33;
742 err = _idt82p33_settime(channel, ts);
748 static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
752 channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
753 channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
754 channel->dpll_tod_sts = DPLL1_TOD_STS;
755 channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
756 channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
757 channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
758 channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
759 channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
762 channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
763 channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
764 channel->dpll_tod_sts = DPLL2_TOD_STS;
765 channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
766 channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
767 channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
768 channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
769 channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
775 INIT_DELAYED_WORK(&channel->sync_tod_work,
777 channel->sync_tod_on = false;
778 channel->current_freq_ppb = 0;
796 struct idt82p33_channel *channel;
802 channel = &idt82p33->channel[index];
804 err = idt82p33_channel_init(channel, index);
808 channel->idt82p33 = idt82p33;
810 idt82p33_caps_init(&channel->caps);
811 snprintf(channel->caps.name, sizeof(channel->caps.name),
813 channel->caps.n_per_out = hweight8(channel->output_mask);
815 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
819 err = idt82p33_enable_tod(channel);
823 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
825 if (IS_ERR(channel->ptp_clock)) {
826 err = PTR_ERR(channel->ptp_clock);
827 channel->ptp_clock = NULL;
831 if (!channel->ptp_clock)
835 index, channel->ptp_clock->index);
923 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
924 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;