Lines Matching defs:channel
38 struct idtcm_channel *channel =
41 channel->write_phase_ready = 1;
264 static int _idtcm_gettime(struct idtcm_channel *channel,
267 struct idtcm *idtcm = channel->idtcm;
273 err = idtcm_read(idtcm, channel->tod_read_primary,
282 err = idtcm_write(idtcm, channel->tod_read_primary,
293 err = idtcm_read(idtcm, channel->tod_read_primary,
304 err = idtcm_read(idtcm, channel->tod_read_primary,
466 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
468 struct idtcm *idtcm = channel->idtcm;
479 u16 output_mask = channel->output_mask;
481 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
550 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
554 struct idtcm *idtcm = channel->idtcm;
563 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
572 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
585 err = idtcm_write(idtcm, channel->hw_dpll_n,
595 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
617 err = idtcm_write(idtcm, channel->hw_dpll_n,
624 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
629 struct idtcm *idtcm = channel->idtcm;
641 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
647 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
657 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
668 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
686 static int _idtcm_settime(struct idtcm_channel *channel,
690 struct idtcm *idtcm = channel->idtcm;
695 err = _idtcm_set_dpll_hw_tod(channel, ts, wr_trig);
702 err = idtcm_read(idtcm, channel->hw_dpll_n,
723 return idtcm_sync_pps_output(channel);
726 static int _idtcm_settime_v487(struct idtcm_channel *channel,
730 return _idtcm_set_dpll_scsr_tod(channel, ts,
735 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
740 struct idtcm *idtcm = channel->idtcm;
749 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
755 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
760 struct idtcm *idtcm = channel->idtcm;
772 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
778 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
781 struct idtcm *idtcm = channel->idtcm;
785 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
793 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
802 static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
808 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
813 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
818 err = idtcm_start_phase_pull_in(channel);
823 static int set_tod_write_overhead(struct idtcm_channel *channel)
825 struct idtcm *idtcm = channel->idtcm;
837 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
844 err = idtcm_write(idtcm, channel->hw_dpll_n,
867 static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
870 struct idtcm *idtcm = channel->idtcm;
875 err = idtcm_do_phase_pull_in(channel, delta, 0);
879 err = set_tod_write_overhead(channel);
884 err = _idtcm_gettime(channel, &ts);
894 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
969 SET_U16_LSB(idtcm->channel[0].output_mask, val);
972 SET_U16_MSB(idtcm->channel[0].output_mask, val);
975 SET_U16_LSB(idtcm->channel[1].output_mask, val);
978 SET_U16_MSB(idtcm->channel[1].output_mask, val);
981 SET_U16_LSB(idtcm->channel[2].output_mask, val);
984 SET_U16_MSB(idtcm->channel[2].output_mask, val);
987 SET_U16_LSB(idtcm->channel[3].output_mask, val);
990 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1012 idtcm->channel[index].pll = pll;
1066 i, idtcm->channel[i].pll,
1067 idtcm->channel[i].output_mask);
1150 static int idtcm_output_enable(struct idtcm_channel *channel,
1153 struct idtcm *idtcm = channel->idtcm;
1172 static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1179 mask = channel->output_mask;
1186 err = idtcm_output_enable(channel, enable, outn);
1199 static int idtcm_perout_enable(struct idtcm_channel *channel,
1206 return idtcm_output_mask_enable(channel, enable);
1209 return idtcm_output_enable(channel, enable, perout->index);
1212 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1215 struct idtcm *idtcm = channel->idtcm;
1219 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1228 channel->pll_mode = pll_mode;
1230 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1247 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1249 struct idtcm *idtcm = channel->idtcm;
1257 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1259 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1264 channel->write_phase_ready = 0;
1266 ptp_schedule_worker(channel->ptp_clock,
1270 if (!channel->write_phase_ready)
1292 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1298 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1300 struct idtcm *idtcm = channel->idtcm;
1307 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
1308 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1344 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1352 struct idtcm_channel *channel =
1354 struct idtcm *idtcm = channel->idtcm;
1359 err = _idtcm_gettime(channel, ts);
1375 struct idtcm_channel *channel =
1377 struct idtcm *idtcm = channel->idtcm;
1382 err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
1398 struct idtcm_channel *channel =
1400 struct idtcm *idtcm = channel->idtcm;
1405 err = _idtcm_settime_v487(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1420 struct idtcm_channel *channel =
1422 struct idtcm *idtcm = channel->idtcm;
1427 err = _idtcm_adjtime(channel, delta);
1442 struct idtcm_channel *channel =
1444 struct idtcm *idtcm = channel->idtcm;
1450 err = idtcm_do_phase_pull_in(channel, delta, 0);
1469 err = _idtcm_settime_v487(channel, &ts, type);
1484 struct idtcm_channel *channel =
1487 struct idtcm *idtcm = channel->idtcm;
1493 err = _idtcm_adjphase(channel, delta);
1508 struct idtcm_channel *channel =
1511 struct idtcm *idtcm = channel->idtcm;
1517 err = _idtcm_adjfine(channel, scaled_ppm);
1535 struct idtcm_channel *channel =
1541 err = idtcm_perout_enable(channel, false, &rq->perout);
1543 dev_err(&channel->idtcm->client->dev,
1555 err = idtcm_perout_enable(channel, true, &rq->perout);
1557 dev_err(&channel->idtcm->client->dev,
1683 static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1685 struct idtcm *idtcm = channel->idtcm;
1693 u16 output_mask = channel->output_mask;
1701 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1707 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1711 switch (channel->tod_n) {
1793 static int idtcm_enable_tod(struct idtcm_channel *channel)
1795 struct idtcm *idtcm = channel->idtcm;
1803 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1809 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1813 return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
1868 static int configure_channel_pll(struct idtcm_channel *channel)
1872 switch (channel->pll) {
1874 channel->dpll_freq = DPLL_FREQ_0;
1875 channel->dpll_n = DPLL_0;
1876 channel->hw_dpll_n = HW_DPLL_0;
1877 channel->dpll_phase = DPLL_PHASE_0;
1878 channel->dpll_ctrl_n = DPLL_CTRL_0;
1879 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1882 channel->dpll_freq = DPLL_FREQ_1;
1883 channel->dpll_n = DPLL_1;
1884 channel->hw_dpll_n = HW_DPLL_1;
1885 channel->dpll_phase = DPLL_PHASE_1;
1886 channel->dpll_ctrl_n = DPLL_CTRL_1;
1887 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1890 channel->dpll_freq = DPLL_FREQ_2;
1891 channel->dpll_n = DPLL_2;
1892 channel->hw_dpll_n = HW_DPLL_2;
1893 channel->dpll_phase = DPLL_PHASE_2;
1894 channel->dpll_ctrl_n = DPLL_CTRL_2;
1895 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
1898 channel->dpll_freq = DPLL_FREQ_3;
1899 channel->dpll_n = DPLL_3;
1900 channel->hw_dpll_n = HW_DPLL_3;
1901 channel->dpll_phase = DPLL_PHASE_3;
1902 channel->dpll_ctrl_n = DPLL_CTRL_3;
1903 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
1906 channel->dpll_freq = DPLL_FREQ_4;
1907 channel->dpll_n = DPLL_4;
1908 channel->hw_dpll_n = HW_DPLL_4;
1909 channel->dpll_phase = DPLL_PHASE_4;
1910 channel->dpll_ctrl_n = DPLL_CTRL_4;
1911 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
1914 channel->dpll_freq = DPLL_FREQ_5;
1915 channel->dpll_n = DPLL_5;
1916 channel->hw_dpll_n = HW_DPLL_5;
1917 channel->dpll_phase = DPLL_PHASE_5;
1918 channel->dpll_ctrl_n = DPLL_CTRL_5;
1919 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
1922 channel->dpll_freq = DPLL_FREQ_6;
1923 channel->dpll_n = DPLL_6;
1924 channel->hw_dpll_n = HW_DPLL_6;
1925 channel->dpll_phase = DPLL_PHASE_6;
1926 channel->dpll_ctrl_n = DPLL_CTRL_6;
1927 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
1930 channel->dpll_freq = DPLL_FREQ_7;
1931 channel->dpll_n = DPLL_7;
1932 channel->hw_dpll_n = HW_DPLL_7;
1933 channel->dpll_phase = DPLL_PHASE_7;
1934 channel->dpll_ctrl_n = DPLL_CTRL_7;
1935 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
1946 struct idtcm_channel *channel;
1952 channel = &idtcm->channel[index];
1955 err = configure_channel_pll(channel);
1962 channel->tod_read_primary = TOD_READ_PRIMARY_0;
1963 channel->tod_write = TOD_WRITE_0;
1964 channel->tod_n = TOD_0;
1967 channel->tod_read_primary = TOD_READ_PRIMARY_1;
1968 channel->tod_write = TOD_WRITE_1;
1969 channel->tod_n = TOD_1;
1972 channel->tod_read_primary = TOD_READ_PRIMARY_2;
1973 channel->tod_write = TOD_WRITE_2;
1974 channel->tod_n = TOD_2;
1977 channel->tod_read_primary = TOD_READ_PRIMARY_3;
1978 channel->tod_write = TOD_WRITE_3;
1979 channel->tod_n = TOD_3;
1985 channel->idtcm = idtcm;
1988 channel->caps = idtcm_caps_v487;
1990 channel->caps = idtcm_caps;
1992 snprintf(channel->caps.name, sizeof(channel->caps.name),
1996 err = idtcm_enable_tod_sync(channel);
2006 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
2015 err = idtcm_enable_tod(channel);
2024 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2026 if (IS_ERR(channel->ptp_clock)) {
2027 err = PTR_ERR(channel->ptp_clock);
2028 channel->ptp_clock = NULL;
2032 if (!channel->ptp_clock)
2035 channel->write_phase_ready = 0;
2038 index, channel->ptp_clock->index);
2046 struct idtcm_channel *channel;
2050 channel = &idtcm->channel[i];
2052 if (channel->ptp_clock)
2053 ptp_clock_unregister(channel->ptp_clock);
2061 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2062 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2063 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2064 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2066 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2067 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2068 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2069 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2078 char *fmt = "Failed at %d in line %s with channel output %d!\n";