Lines Matching refs:fifo
68 * @fifo: pointer to the tmfifo structure
85 struct mlxbf_tmfifo *fifo;
139 * @fifo: pointer to the tmfifo structure
144 struct mlxbf_tmfifo *fifo;
218 static void mlxbf_tmfifo_free_vrings(struct mlxbf_tmfifo *fifo,
240 static int mlxbf_tmfifo_alloc_vrings(struct mlxbf_tmfifo *fifo,
251 vring->fifo = fifo;
262 mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
275 static void mlxbf_tmfifo_disable_irqs(struct mlxbf_tmfifo *fifo)
280 irq = fifo->irq_info[i].irq;
281 fifo->irq_info[i].irq = 0;
291 if (!test_and_set_bit(irq_info->index, &irq_info->fifo->pend_events))
292 schedule_work(&irq_info->fifo->work);
412 struct mlxbf_tmfifo *fifo = container_of(t, struct mlxbf_tmfifo, timer);
415 rx = !test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events);
416 tx = !test_and_set_bit(MLXBF_TM_TX_LWM_IRQ, &fifo->pend_events);
419 schedule_work(&fifo->work);
421 mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
482 static int mlxbf_tmfifo_get_rx_avail(struct mlxbf_tmfifo *fifo)
486 sts = readq(fifo->rx_base + MLXBF_TMFIFO_RX_STS);
491 static int mlxbf_tmfifo_get_tx_avail(struct mlxbf_tmfifo *fifo, int vdev_id)
499 tx_reserve = fifo->tx_fifo_size / MLXBF_TMFIFO_RESERVE_RATIO;
503 sts = readq(fifo->tx_base + MLXBF_TMFIFO_TX_STS);
505 return fifo->tx_fifo_size - tx_reserve - count;
509 static void mlxbf_tmfifo_console_tx(struct mlxbf_tmfifo *fifo, int avail)
522 cons = fifo->vdev[VIRTIO_ID_CONSOLE];
539 writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
542 spin_lock_irqsave(&fifo->spin_lock[0], flags);
556 writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
569 spin_unlock_irqrestore(&fifo->spin_lock[0], flags);
578 struct mlxbf_tmfifo *fifo = vring->fifo;
587 data = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
616 writeq(data, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
630 struct mlxbf_tmfifo *fifo = vring->fifo;
639 *(u64 *)&hdr = readq(fifo->rx_base + MLXBF_TMFIFO_RX_DATA);
649 config = &fifo->vdev[vdev_id]->config.net;
666 struct mlxbf_tmfifo_vdev *tm_dev2 = fifo->vdev[vdev_id];
692 writeq(*(u64 *)&hdr, fifo->tx_base + MLXBF_TMFIFO_TX_DATA);
697 fifo->vring[is_rx] = vring;
709 struct mlxbf_tmfifo *fifo = vring->fifo;
716 vdev = &fifo->vdev[vring->vdev_id]->vdev;
772 fifo->vring[is_rx] = NULL;
789 spin_lock_irqsave(&fifo->spin_lock[is_rx], flags);
791 spin_unlock_irqrestore(&fifo->spin_lock[is_rx], flags);
805 struct mlxbf_tmfifo *fifo;
808 fifo = vring->fifo;
811 if (!fifo->vdev[devid])
815 if (fifo->vring[is_rx] && fifo->vring[is_rx] != vring)
826 avail = mlxbf_tmfifo_get_rx_avail(fifo);
828 avail = mlxbf_tmfifo_get_tx_avail(fifo, devid);
835 mlxbf_tmfifo_console_tx(fifo, avail);
845 static void mlxbf_tmfifo_work_rxtx(struct mlxbf_tmfifo *fifo, int queue_id,
852 if (!test_and_clear_bit(irq_id, &fifo->pend_events) ||
853 !fifo->irq_info[irq_id].irq)
857 tm_vdev = fifo->vdev[i];
869 struct mlxbf_tmfifo *fifo;
871 fifo = container_of(work, struct mlxbf_tmfifo, work);
872 if (!fifo->is_ready)
875 mutex_lock(&fifo->lock);
878 mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_TX,
882 mlxbf_tmfifo_work_rxtx(fifo, MLXBF_TMFIFO_VRING_RX,
885 mutex_unlock(&fifo->lock);
893 struct mlxbf_tmfifo *fifo;
896 fifo = vring->fifo;
910 spin_lock_irqsave(&fifo->spin_lock[0], flags);
911 tm_vdev = fifo->vdev[VIRTIO_ID_CONSOLE];
913 spin_unlock_irqrestore(&fifo->spin_lock[0], flags);
914 set_bit(MLXBF_TM_TX_LWM_IRQ, &fifo->pend_events);
916 &fifo->pend_events)) {
920 if (test_and_set_bit(MLXBF_TM_RX_HWM_IRQ, &fifo->pend_events))
924 schedule_work(&fifo->work);
1095 struct mlxbf_tmfifo *fifo,
1102 mutex_lock(&fifo->lock);
1104 tm_vdev = fifo->vdev[vdev_id];
1125 if (mlxbf_tmfifo_alloc_vrings(fifo, tm_vdev)) {
1136 fifo->vdev[vdev_id] = tm_vdev;
1146 mutex_unlock(&fifo->lock);
1150 mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
1151 fifo->vdev[vdev_id] = NULL;
1157 mutex_unlock(&fifo->lock);
1162 static int mlxbf_tmfifo_delete_vdev(struct mlxbf_tmfifo *fifo, int vdev_id)
1166 mutex_lock(&fifo->lock);
1169 tm_vdev = fifo->vdev[vdev_id];
1172 mlxbf_tmfifo_free_vrings(fifo, tm_vdev);
1173 fifo->vdev[vdev_id] = NULL;
1176 mutex_unlock(&fifo->lock);
1197 static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo)
1202 ctl = readq(fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
1203 fifo->tx_fifo_size =
1207 fifo->tx_fifo_size / 2);
1210 fifo->tx_fifo_size - 1);
1211 writeq(ctl, fifo->tx_base + MLXBF_TMFIFO_TX_CTL);
1214 ctl = readq(fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
1215 fifo->rx_fifo_size =
1221 writeq(ctl, fifo->rx_base + MLXBF_TMFIFO_RX_CTL);
1224 static void mlxbf_tmfifo_cleanup(struct mlxbf_tmfifo *fifo)
1228 fifo->is_ready = false;
1229 del_timer_sync(&fifo->timer);
1230 mlxbf_tmfifo_disable_irqs(fifo);
1231 cancel_work_sync(&fifo->work);
1233 mlxbf_tmfifo_delete_vdev(fifo, i);
1241 struct mlxbf_tmfifo *fifo;
1244 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
1245 if (!fifo)
1248 spin_lock_init(&fifo->spin_lock[0]);
1249 spin_lock_init(&fifo->spin_lock[1]);
1250 INIT_WORK(&fifo->work, mlxbf_tmfifo_work_handler);
1251 mutex_init(&fifo->lock);
1254 fifo->rx_base = devm_platform_ioremap_resource(pdev, 0);
1255 if (IS_ERR(fifo->rx_base))
1256 return PTR_ERR(fifo->rx_base);
1259 fifo->tx_base = devm_platform_ioremap_resource(pdev, 1);
1260 if (IS_ERR(fifo->tx_base))
1261 return PTR_ERR(fifo->tx_base);
1263 platform_set_drvdata(pdev, fifo);
1265 timer_setup(&fifo->timer, mlxbf_tmfifo_timer, 0);
1268 fifo->irq_info[i].index = i;
1269 fifo->irq_info[i].fifo = fifo;
1270 fifo->irq_info[i].irq = platform_get_irq(pdev, i);
1271 rc = devm_request_irq(dev, fifo->irq_info[i].irq,
1273 "tmfifo", &fifo->irq_info[i]);
1276 fifo->irq_info[i].irq = 0;
1281 mlxbf_tmfifo_set_threshold(fifo);
1284 rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_CONSOLE, 0, NULL, 0);
1297 rc = mlxbf_tmfifo_create_vdev(dev, fifo, VIRTIO_ID_NET,
1303 mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL);
1305 fifo->is_ready = true;
1309 mlxbf_tmfifo_cleanup(fifo);
1316 struct mlxbf_tmfifo *fifo = platform_get_drvdata(pdev);
1318 mlxbf_tmfifo_cleanup(fifo);