Lines Matching refs:TOP_PIN
468 TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
472 TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
476 TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
480 TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
484 TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
488 TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
492 TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
496 TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
500 TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
504 TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
508 TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
512 TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
516 TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
520 TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
524 TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
528 TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
534 TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
538 TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
542 TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
547 TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
552 TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
557 TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
562 TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
567 TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
572 TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
577 TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
582 TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
585 TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
590 TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
595 TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
600 TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
605 TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
611 TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
615 TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
619 TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
623 TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
630 TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
637 TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
646 TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
653 TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
656 TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
659 TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
662 TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
665 TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
668 TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
671 TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
674 TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
679 TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
683 TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
688 TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
693 TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
698 TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
703 TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
708 TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
713 TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
718 TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
723 TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
728 TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
733 TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
740 TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
747 TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
756 TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
763 TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
770 TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
777 TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
784 TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
791 TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
796 TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
801 TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
806 TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
815 TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
824 TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
833 TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
838 TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
847 TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
854 TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
861 TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
868 TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
875 TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
880 TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
888 TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
896 TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
903 TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
910 TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
919 TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
926 TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
933 TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
940 TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
947 TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
954 TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
960 TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
966 TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
973 TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
982 TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
987 TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
992 TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
994 TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,