Lines Matching defs:REG_PINMUX2
21 #define REG_PINMUX2 0x3004
164 VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022),
165 VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200),
176 VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000),
177 VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000),
183 VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111),
184 VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000),
189 VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000),
193 VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000),
194 VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000),
195 VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000),
196 VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000),
281 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)),
282 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)),
283 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)),
284 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)),
285 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)),
286 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)),
287 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)),
288 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)),