Lines Matching refs:pctl
50 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
54 for (i = 0; i < pctl->ngroups; i++) {
55 struct sunxi_pinctrl_group *grp = pctl->groups + i;
65 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
68 struct sunxi_pinctrl_function *func = pctl->functions;
71 for (i = 0; i < pctl->nfunctions; i++) {
83 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
89 for (i = 0; i < pctl->desc->npins; i++) {
90 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
98 func->variant & pctl->variant))
110 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
116 for (i = 0; i < pctl->desc->npins; i++) {
117 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
136 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138 return pctl->ngroups;
144 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
146 return pctl->groups[group].name;
154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
156 *pins = (unsigned *)&pctl->groups[group].pin;
332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
344 dev_err(pctl->dev, "missing function property in node %pOFn\n",
351 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
376 sunxi_pinctrl_find_group_by_name(pctl, group);
379 dev_err(pctl->dev, "unknown pin %s", group);
383 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
386 dev_err(pctl->dev, "unsupported function %s on pin %s",
482 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
488 pin -= pctl->desc->pin_base;
494 val = (readl(pctl->membase + offset) >> shift) & mask;
534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
535 struct sunxi_pinctrl_group *g = &pctl->groups[group];
544 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
547 pin -= pctl->desc->pin_base;
595 raw_spin_lock_irqsave(&pctl->lock, flags);
596 reg = readl(pctl->membase + offset);
598 writel(reg | val << shift, pctl->membase + offset);
599 raw_spin_unlock_irqrestore(&pctl->lock, flags);
608 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
609 struct sunxi_pinctrl_group *g = &pctl->groups[group];
623 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
632 if (!pctl->desc->io_bias_cfg_variant)
643 pin -= pctl->desc->pin_base;
646 switch (pctl->desc->io_bias_cfg_variant) {
663 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
665 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
670 raw_spin_lock_irqsave(&pctl->lock, flags);
671 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
673 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
674 raw_spin_unlock_irqrestore(&pctl->lock, flags);
683 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
685 return pctl->nfunctions;
691 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
693 return pctl->functions[function].name;
701 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
703 *groups = pctl->functions[function].groups;
704 *num_groups = pctl->functions[function].ngroups;
713 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
717 raw_spin_lock_irqsave(&pctl->lock, flags);
719 pin -= pctl->desc->pin_base;
720 val = readl(pctl->membase + sunxi_mux_reg(pin));
723 pctl->membase + sunxi_mux_reg(pin));
725 raw_spin_unlock_irqrestore(&pctl->lock, flags);
732 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
733 struct sunxi_pinctrl_group *g = pctl->groups + group;
734 struct sunxi_pinctrl_function *func = pctl->functions + function;
736 sunxi_pinctrl_desc_find_function_by_name(pctl,
754 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
763 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
774 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
776 unsigned short bank_offset = bank - pctl->desc->pin_base /
778 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
789 reg = regulator_get(pctl->dev, supply);
791 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
798 dev_err(pctl->dev,
803 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
818 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
820 unsigned short bank_offset = bank - pctl->desc->pin_base /
822 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
853 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
856 bool set_mux = pctl->desc->irq_read_needs_mux &&
862 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
864 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
867 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
875 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
881 raw_spin_lock_irqsave(&pctl->lock, flags);
883 regval = readl(pctl->membase + reg);
890 writel(regval, pctl->membase + reg);
892 raw_spin_unlock_irqrestore(&pctl->lock, flags);
922 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
924 unsigned pinnum = pctl->desc->pin_base + offset;
930 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
939 return irq_find_mapping(pctl->domain, irqnum);
944 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
948 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
949 pctl->irq_array[d->hwirq], "irq");
953 ret = gpiochip_lock_as_irq(pctl->chip,
954 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
956 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
962 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
969 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
971 gpiochip_unlock_as_irq(pctl->chip,
972 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
977 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
978 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
1004 raw_spin_lock_irqsave(&pctl->lock, flags);
1013 regval = readl(pctl->membase + reg);
1015 writel(regval | (mode << index), pctl->membase + reg);
1017 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1024 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1025 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1029 writel(1 << status_idx, pctl->membase + status_reg);
1034 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1035 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1040 raw_spin_lock_irqsave(&pctl->lock, flags);
1043 val = readl(pctl->membase + reg);
1044 writel(val & ~(1 << idx), pctl->membase + reg);
1046 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1051 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1052 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1057 raw_spin_lock_irqsave(&pctl->lock, flags);
1060 val = readl(pctl->membase + reg);
1061 writel(val | (1 << idx), pctl->membase + reg);
1063 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1074 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1077 return irq_set_irq_wake(pctl->irq[bank], on);
1117 struct sunxi_pinctrl *pctl = d->host_data;
1125 pin = pctl->desc->pin_base + base + intspec[1];
1127 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1145 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1148 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1149 if (irq == pctl->irq[bank])
1152 if (bank == pctl->desc->irq_banks)
1157 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1158 val = readl(pctl->membase + reg);
1164 int pin_irq = irq_find_mapping(pctl->domain,
1173 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1176 struct sunxi_pinctrl_function *func = pctl->functions;
1190 pctl->nfunctions++;
1197 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1212 pctl->groups = devm_kcalloc(&pdev->dev,
1213 pctl->desc->npins, sizeof(*pctl->groups),
1215 if (!pctl->groups)
1218 for (i = 0; i < pctl->desc->npins; i++) {
1219 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1220 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1222 if (pin->variant && !(pctl->variant & pin->variant))
1229 pctl->ngroups++;
1236 pctl->functions = kcalloc(pctl->ngroups,
1237 sizeof(*pctl->functions),
1239 if (!pctl->functions)
1243 for (i = 0; i < pctl->desc->npins; i++) {
1244 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1247 if (pin->variant && !(pctl->variant & pin->variant))
1251 if (func->variant && !(pctl->variant & func->variant))
1257 pctl->irq_array[irqnum] = pin->pin.number;
1260 sunxi_pinctrl_add_function(pctl, func->name);
1265 ptr = krealloc(pctl->functions,
1266 pctl->nfunctions * sizeof(*pctl->functions),
1269 kfree(pctl->functions);
1270 pctl->functions = NULL;
1273 pctl->functions = ptr;
1275 for (i = 0; i < pctl->desc->npins; i++) {
1276 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1279 if (pin->variant && !(pctl->variant & pin->variant))
1286 if (func->variant && !(pctl->variant & func->variant))
1289 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1292 kfree(pctl->functions);
1303 kfree(pctl->functions);
1341 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1358 losc = devm_clk_get(pctl->dev, "losc");
1362 hosc = devm_clk_get(pctl->dev, "hosc");
1366 for (i = 0; i < pctl->desc->irq_banks; i++) {
1396 pctl->membase +
1397 sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1410 struct sunxi_pinctrl *pctl;
1415 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1416 if (!pctl)
1418 platform_set_drvdata(pdev, pctl);
1420 raw_spin_lock_init(&pctl->lock);
1422 pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1423 if (IS_ERR(pctl->membase))
1424 return PTR_ERR(pctl->membase);
1426 pctl->dev = &pdev->dev;
1427 pctl->desc = desc;
1428 pctl->variant = variant;
1430 pctl->irq_array = devm_kcalloc(&pdev->dev,
1431 IRQ_PER_BANK * pctl->desc->irq_banks,
1432 sizeof(*pctl->irq_array),
1434 if (!pctl->irq_array)
1444 pctl->desc->npins, sizeof(*pins),
1449 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1450 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1452 if (pin->variant && !(pctl->variant & pin->variant))
1467 pctrl_desc->npins = pctl->ngroups;
1481 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1482 if (IS_ERR(pctl->pctl_dev)) {
1484 return PTR_ERR(pctl->pctl_dev);
1487 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1488 if (!pctl->chip)
1491 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1492 pctl->chip->owner = THIS_MODULE;
1493 pctl->chip->request = gpiochip_generic_request;
1494 pctl->chip->free = gpiochip_generic_free;
1495 pctl->chip->set_config = gpiochip_generic_config;
1496 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1497 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1498 pctl->chip->get = sunxi_pinctrl_gpio_get;
1499 pctl->chip->set = sunxi_pinctrl_gpio_set;
1500 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1501 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1502 pctl->chip->of_gpio_n_cells = 3;
1503 pctl->chip->can_sleep = false;
1504 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1505 pctl->desc->pin_base;
1506 pctl->chip->label = dev_name(&pdev->dev);
1507 pctl->chip->parent = &pdev->dev;
1508 pctl->chip->base = pctl->desc->pin_base;
1510 ret = gpiochip_add_data(pctl->chip, pctl);
1514 for (i = 0; i < pctl->desc->npins; i++) {
1515 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1517 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1518 pin->pin.number - pctl->desc->pin_base,
1535 pctl->irq = devm_kcalloc(&pdev->dev,
1536 pctl->desc->irq_banks,
1537 sizeof(*pctl->irq),
1539 if (!pctl->irq) {
1544 for (i = 0; i < pctl->desc->irq_banks; i++) {
1545 pctl->irq[i] = platform_get_irq(pdev, i);
1546 if (pctl->irq[i] < 0) {
1547 ret = pctl->irq[i];
1552 pctl->domain = irq_domain_add_linear(node,
1553 pctl->desc->irq_banks * IRQ_PER_BANK,
1555 pctl);
1556 if (!pctl->domain) {
1562 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1563 int irqno = irq_create_mapping(pctl->domain, i);
1569 irq_set_chip_data(irqno, pctl);
1572 for (i = 0; i < pctl->desc->irq_banks; i++) {
1574 writel(0, pctl->membase +
1575 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1577 pctl->membase +
1578 sunxi_irq_status_reg_from_bank(pctl->desc, i));
1580 irq_set_chained_handler_and_data(pctl->irq[i],
1582 pctl);
1585 sunxi_pinctrl_setup_debounce(pctl, node);
1594 gpiochip_remove(pctl->chip);