Lines Matching refs:bank
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
195 stm32_gpio_backup_value(bank, offset, value);
200 clk_enable(bank->clk);
202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
204 clk_disable(bank->clk);
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
240 clk_enable(bank->clk);
244 clk_disable(bank->clk);
251 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
253 __stm32_gpio_set(bank, offset, value);
264 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
266 __stm32_gpio_set(bank, offset, value);
275 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
278 fwspec.fwnode = bank->fwnode;
288 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
293 stm32_pmx_get_mode(bank, pin, &mode, &alt);
318 struct stm32_gpio_bank *bank = d->domain->host_data;
322 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
326 level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq);
327 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
328 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
340 struct stm32_gpio_bank *bank = d->domain->host_data;
359 bank->irq_type[d->hwirq] = type;
366 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
367 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
371 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
375 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
384 clk_enable(bank->clk);
391 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
393 if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK)
394 clk_disable(bank->clk);
396 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
434 struct stm32_gpio_bank *bank = d->host_data;
435 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
465 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
478 struct stm32_gpio_bank *bank = d->host_data;
479 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
491 struct stm32_gpio_bank *bank = d->host_data;
503 bank);
763 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
766 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
773 clk_enable(bank->clk);
774 spin_lock_irqsave(&bank->lock, flags);
785 val = readl_relaxed(bank->base + alt_offset);
788 writel_relaxed(val, bank->base + alt_offset);
790 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
793 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
798 stm32_gpio_backup_mode(bank, pin, mode, alt);
801 spin_unlock_irqrestore(&bank->lock, flags);
802 clk_disable(bank->clk);
807 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
815 clk_enable(bank->clk);
816 spin_lock_irqsave(&bank->lock, flags);
818 val = readl_relaxed(bank->base + alt_offset);
822 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
826 spin_unlock_irqrestore(&bank->lock, flags);
827 clk_disable(bank->clk);
838 struct stm32_gpio_bank *bank;
855 bank = gpiochip_get_data(range->gc);
861 return stm32_pmx_set_mode(bank, pin, mode, alt);
868 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
871 return stm32_pmx_set_mode(bank, pin, !input, 0);
885 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
888 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
893 clk_enable(bank->clk);
894 spin_lock_irqsave(&bank->lock, flags);
905 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
908 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
913 stm32_gpio_backup_driving(bank, offset, drive);
916 spin_unlock_irqrestore(&bank->lock, flags);
917 clk_disable(bank->clk);
922 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
928 clk_enable(bank->clk);
929 spin_lock_irqsave(&bank->lock, flags);
931 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
934 spin_unlock_irqrestore(&bank->lock, flags);
935 clk_disable(bank->clk);
940 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
943 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
948 clk_enable(bank->clk);
949 spin_lock_irqsave(&bank->lock, flags);
960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
963 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
968 stm32_gpio_backup_speed(bank, offset, speed);
971 spin_unlock_irqrestore(&bank->lock, flags);
972 clk_disable(bank->clk);
977 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
983 clk_enable(bank->clk);
984 spin_lock_irqsave(&bank->lock, flags);
986 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
989 spin_unlock_irqrestore(&bank->lock, flags);
990 clk_disable(bank->clk);
995 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
998 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1003 clk_enable(bank->clk);
1004 spin_lock_irqsave(&bank->lock, flags);
1015 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1018 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1023 stm32_gpio_backup_bias(bank, offset, bias);
1026 spin_unlock_irqrestore(&bank->lock, flags);
1027 clk_disable(bank->clk);
1032 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1038 clk_enable(bank->clk);
1039 spin_lock_irqsave(&bank->lock, flags);
1041 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1044 spin_unlock_irqrestore(&bank->lock, flags);
1045 clk_disable(bank->clk);
1050 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1056 clk_enable(bank->clk);
1057 spin_lock_irqsave(&bank->lock, flags);
1060 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1063 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1066 spin_unlock_irqrestore(&bank->lock, flags);
1067 clk_disable(bank->clk);
1078 struct stm32_gpio_bank *bank;
1087 bank = gpiochip_get_data(range->gc);
1092 ret = stm32_pconf_set_driving(bank, offset, 0);
1095 ret = stm32_pconf_set_driving(bank, offset, 1);
1098 ret = stm32_pconf_set_speed(bank, offset, arg);
1101 ret = stm32_pconf_set_bias(bank, offset, 0);
1104 ret = stm32_pconf_set_bias(bank, offset, 1);
1107 ret = stm32_pconf_set_bias(bank, offset, 2);
1110 __stm32_gpio_set(bank, offset, arg);
1174 struct stm32_gpio_bank *bank;
1189 bank = gpiochip_get_data(range->gc);
1192 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1193 bias = stm32_pconf_get_bias(bank, offset);
1200 val = stm32_pconf_get(bank, offset, true);
1208 drive = stm32_pconf_get_driving(bank, offset);
1209 speed = stm32_pconf_get_speed(bank, offset);
1210 val = stm32_pconf_get(bank, offset, false);
1220 drive = stm32_pconf_get_driving(bank, offset);
1221 speed = stm32_pconf_get_speed(bank, offset);
1244 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1246 struct pinctrl_gpio_range *range = &bank->range;
1253 if (!IS_ERR(bank->rstc))
1254 reset_control_deassert(bank->rstc);
1259 bank->base = devm_ioremap_resource(dev, &res);
1260 if (IS_ERR(bank->base))
1261 return PTR_ERR(bank->base);
1263 err = clk_prepare(bank->clk);
1269 bank->gpio_chip = stm32_gpio_template;
1271 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1275 bank->gpio_chip.base = args.args[1];
1283 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1284 range->name = bank->gpio_chip.label;
1289 range->gc = &bank->gpio_chip;
1294 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1297 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1299 bank->gpio_chip.ngpio = npins;
1300 bank->gpio_chip.of_node = np;
1301 bank->gpio_chip.parent = dev;
1302 bank->bank_nr = bank_nr;
1303 bank->bank_ioport_nr = bank_ioport_nr;
1304 spin_lock_init(&bank->lock);
1308 bank->fwnode = of_node_to_fwnode(np);
1310 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1311 bank->fwnode, &stm32_gpio_domain_ops,
1312 bank);
1314 if (!bank->domain)
1318 err = gpiochip_add_data(&bank->gpio_chip, bank);
1324 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1559 dev_err(dev, "at least one GPIO bank is required\n");
1569 struct stm32_gpio_bank *bank = &pctl->banks[i];
1572 bank->rstc = of_reset_control_get_exclusive(child,
1574 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)
1577 bank->clk = of_clk_get_by_name(child, NULL);
1578 if (IS_ERR(bank->clk)) {
1579 if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1582 PTR_ERR(bank->clk));
1583 return PTR_ERR(bank->clk);
1612 struct stm32_gpio_bank *bank;
1625 bank = gpiochip_get_data(range->gc);
1627 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1629 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1632 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1637 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1639 __stm32_gpio_set(bank, offset, val);
1642 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1644 ret = stm32_pconf_set_driving(bank, offset, val);
1648 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1650 ret = stm32_pconf_set_speed(bank, offset, val);
1654 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1656 ret = stm32_pconf_set_bias(bank, offset, val);
1661 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);