Lines Matching defs:pctl
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
216 dev_err(pctl->dev, "pin %d not in range.\n", pin);
367 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
377 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
435 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
443 spin_lock_irqsave(&pctl->irqmux_lock, flags);
445 if (pctl->hwlock) {
446 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
449 dev_err(pctl->dev, "Can't get hwspinlock\n");
454 if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
455 dev_err(pctl->dev, "irq line %ld already requested.\n",
458 if (pctl->hwlock)
459 hwspin_unlock_in_atomic(pctl->hwlock);
462 pctl->irqmux_map |= BIT(irq_data->hwirq);
465 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
467 if (pctl->hwlock)
468 hwspin_unlock_in_atomic(pctl->hwlock);
471 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
479 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
482 spin_lock_irqsave(&pctl->irqmux_lock, flags);
483 pctl->irqmux_map &= ~BIT(irq_data->hwirq);
484 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
518 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
522 for (i = 0; i < pctl->ngroups; i++) {
523 struct stm32_pinctrl_group *grp = pctl->groups + i;
532 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
537 for (i = 0; i < pctl->npins; i++) {
538 const struct stm32_desc_pin *pin = pctl->pins + i;
556 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
567 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
568 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
585 struct stm32_pinctrl *pctl;
595 pctl = pinctrl_dev_get_drvdata(pctldev);
599 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
641 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
642 dev_err(pctl->dev, "invalid function.\n");
647 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
649 dev_err(pctl->dev, "unable to match pin %d to group\n",
655 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
702 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
704 return pctl->ngroups;
710 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
712 return pctl->groups[group].name;
720 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
722 *pins = (unsigned *)&pctl->groups[group].pin;
755 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
757 *groups = pctl->grp_names;
758 *num_groups = pctl->ngroups;
766 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
776 if (pctl->hwlock) {
777 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
780 dev_err(pctl->dev, "Can't get hwspinlock\n");
795 if (pctl->hwlock)
796 hwspin_unlock_in_atomic(pctl->hwlock);
835 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
836 struct stm32_pinctrl_group *g = pctl->groups + group;
842 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
844 dev_err(pctl->dev, "invalid function %d on group %d .\n",
851 dev_err(pctl->dev, "No gpio range defined.\n");
888 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
896 if (pctl->hwlock) {
897 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
900 dev_err(pctl->dev, "Can't get hwspinlock\n");
910 if (pctl->hwlock)
911 hwspin_unlock_in_atomic(pctl->hwlock);
943 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
951 if (pctl->hwlock) {
952 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
955 dev_err(pctl->dev, "Can't get hwspinlock\n");
965 if (pctl->hwlock)
966 hwspin_unlock_in_atomic(pctl->hwlock);
998 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1006 if (pctl->hwlock) {
1007 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1010 dev_err(pctl->dev, "Can't get hwspinlock\n");
1020 if (pctl->hwlock)
1021 hwspin_unlock_in_atomic(pctl->hwlock);
1076 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1083 dev_err(pctl->dev, "No gpio range defined.\n");
1124 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1126 *config = pctl->groups[group].config;
1134 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1135 struct stm32_pinctrl_group *g = &pctl->groups[group];
1241 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1244 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1248 struct device *dev = pctl->dev;
1282 bank_nr = pctl->nbanks;
1290 pinctrl_add_gpio_range(pctl->pctl_dev,
1291 &pctl->banks[bank_nr].range);
1306 if (pctl->domain) {
1310 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1350 struct stm32_pinctrl *pctl)
1358 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1359 if (IS_ERR(pctl->regmap))
1360 return PTR_ERR(pctl->regmap);
1362 rm = pctl->regmap;
1384 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1385 if (IS_ERR(pctl->irqmux[i]))
1386 return PTR_ERR(pctl->irqmux[i]);
1394 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1397 pctl->ngroups = pctl->npins;
1400 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1401 sizeof(*pctl->groups), GFP_KERNEL);
1402 if (!pctl->groups)
1406 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1407 sizeof(*pctl->grp_names), GFP_KERNEL);
1408 if (!pctl->grp_names)
1411 for (i = 0; i < pctl->npins; i++) {
1412 const struct stm32_desc_pin *pin = pctl->pins + i;
1413 struct stm32_pinctrl_group *group = pctl->groups + i;
1417 pctl->grp_names[i] = pin->pin.name;
1423 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1429 for (i = 0; i < pctl->match_data->npins; i++) {
1430 p = pctl->match_data->pins + i;
1431 if (pctl->pkg && !(pctl->pkg & p->pkg))
1439 pctl->npins = nb_pins_available;
1445 struct stm32_pinctrl *pctl)
1447 if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1448 pctl->pkg = 0;
1449 dev_warn(pctl->dev, "No package detected, use default one\n");
1451 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1461 struct stm32_pinctrl *pctl;
1477 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1478 if (!pctl)
1481 platform_set_drvdata(pdev, pctl);
1484 pctl->domain = stm32_pctrl_get_irq_domain(np);
1485 if (IS_ERR(pctl->domain))
1486 return PTR_ERR(pctl->domain);
1487 if (!pctl->domain)
1496 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1499 spin_lock_init(&pctl->irqmux_lock);
1501 pctl->dev = dev;
1502 pctl->match_data = match->data;
1505 stm32_pctl_get_package(np, pctl);
1507 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1508 sizeof(*pctl->pins), GFP_KERNEL);
1509 if (!pctl->pins)
1512 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1522 if (pctl->domain) {
1523 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1528 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1533 for (i = 0; i < pctl->npins; i++)
1534 pins[i] = pctl->pins[i].pin;
1536 pctl->pctl_desc.name = dev_name(&pdev->dev);
1537 pctl->pctl_desc.owner = THIS_MODULE;
1538 pctl->pctl_desc.pins = pins;
1539 pctl->pctl_desc.npins = pctl->npins;
1540 pctl->pctl_desc.link_consumers = true;
1541 pctl->pctl_desc.confops = &stm32_pconf_ops;
1542 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1543 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1544 pctl->dev = &pdev->dev;
1546 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1547 pctl);
1549 if (IS_ERR(pctl->pctl_dev)) {
1551 return PTR_ERR(pctl->pctl_dev);
1562 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1564 if (!pctl->banks)
1569 struct stm32_gpio_bank *bank = &pctl->banks[i];
1591 ret = stm32_gpiolib_register_bank(pctl, child);
1597 pctl->nbanks++;
1607 struct stm32_pinctrl *pctl, u32 pin)
1609 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1616 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1661 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1668 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1669 struct stm32_pinctrl_group *g = pctl->groups;
1672 for (i = 0; i < pctl->ngroups; i++, g++)
1673 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);