Lines Matching defs:val
220 .val = 0x0,
224 .val = 0x0,
228 .val = 0x0,
232 .val = 0x0,
236 .val = 0x0,
240 .val = 0x0,
244 .val = 0x0,
248 .val = 0x0,
281 .val = FSMC_8BIT_REG7_MASK,
306 .val = 0,
310 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
337 .val = 0,
341 .val = FSMC_PNOR_AND_MCIF_REG6_MASK,
375 .val = KBD_ROW_COL_MASK,
379 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
404 .val = KBD_COL5_MASK,
408 .val = PWM1_AND_KBD_COL5_REG0_MASK,
441 .val = SPDIF_IN_REG0_MASK,
473 .val = SPDIF_OUT_REG4_MASK,
477 .val = SPDIF_OUT_ENB_MASK,
509 .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
515 .val = UART0_ENH_AND_GPT_REG0_MASK |
549 .val = 0,
553 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
578 .val = 0,
582 .val = PWM1_AND_KBD_COL5_REG0_MASK,
607 .val = 0,
611 .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
636 .val = 0,
640 .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
673 .val = VIP_REG1_MASK,
699 .val = 0,
703 .val = VIP_AND_CAM0_REG2_MASK,
729 .val = 0,
733 .val = VIP_AND_CAM1_REG1_MASK,
737 .val = VIP_AND_CAM1_REG2_MASK,
763 .val = 0,
767 .val = VIP_AND_CAM2_REG1_MASK,
793 .val = 0,
797 .val = VIP_AND_CAM3_REG0_MASK,
801 .val = VIP_AND_CAM3_REG1_MASK,
835 .val = CAM0_MASK,
839 .val = VIP_AND_CAM0_REG2_MASK,
872 .val = CAM1_MASK,
876 .val = VIP_AND_CAM1_REG1_MASK,
880 .val = VIP_AND_CAM1_REG2_MASK,
913 .val = CAM2_MASK,
917 .val = VIP_AND_CAM2_REG1_MASK,
950 .val = CAM3_MASK,
954 .val = VIP_AND_CAM3_REG0_MASK,
958 .val = VIP_AND_CAM3_REG1_MASK,
990 .val = SMI_REG2_MASK,
1022 .val = SSP0_REG2_MASK,
1047 .val = SSP0_CS1_MASK,
1051 .val = PWM0_AND_SSP0_CS1_REG0_MASK,
1076 .val = SSP0_CS2_MASK,
1080 .val = TS_AND_SSP0_CS2_REG2_MASK,
1105 .val = SSP0_CS3_REG4_MASK,
1138 .val = UART0_REG2_MASK,
1163 .val = 0,
1167 .val = UART0_ENH_AND_GPT_REG0_MASK,
1199 .val = UART1_REG2_MASK,
1231 .val = I2S_IN_REG2_MASK,
1235 .val = I2S_IN_REG3_MASK,
1260 .val = I2S_OUT_REG3_MASK,
1294 .val = GMAC_REG3_MASK, \
1298 .val = GMAC_REG4_MASK, \
1307 .val = GMAC_PHY_IF_GMII_VAL,
1332 .val = GMAC_PHY_IF_RGMII_VAL,
1357 .val = GMAC_PHY_IF_RMII_VAL,
1382 .val = GMAC_PHY_IF_SGMII_VAL,
1415 .val = I2C0_REG4_MASK,
1447 .val = I2C1_REG0_MASK,
1479 .val = CEC0_REG4_MASK,
1511 .val = CEC1_REG4_MASK,
1546 .val = MCIF_MASK, \
1550 .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1554 .val = MCIF_REG7_MASK, \
1563 .val = MCIF_SEL_SD,
1595 .val = MCIF_SEL_CF,
1627 .val = MCIF_SEL_XD,
1663 .val = 0,
1667 .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1671 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1675 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1699 .val = 0,
1703 .val = 0x0,
1707 .val = 0x0,
1711 .val = 0x0,
1746 .val = ARM_TRACE_MASK,
1750 .val = CLCD_AND_ARM_TRACE_REG4_MASK,
1754 .val = CLCD_AND_ARM_TRACE_REG5_MASK,
1758 .val = CLCD_AND_ARM_TRACE_REG6_MASK,
1792 .val = MIPHY_DBG_MASK,
1796 .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1828 .val = PCIE_CFG_VAL,
1860 .val = SATA_CFG_VAL,
1977 unsigned int val;
1990 val = pmx_readl(pmx, regoffset);
1992 val &= ~(0x1 << bitoffset);
1994 val |= 0x1 << bitoffset;
1996 pmx_writel(pmx, val, regoffset);