Lines Matching refs:sgpio
410 sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
412 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
423 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
424 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
431 spin_lock_irqsave(&sgpio->lock, flags);
433 val = readl(sgpio->chip.regs + offset);
435 writel(val, sgpio->chip.regs + offset);
437 spin_unlock_irqrestore(&sgpio->lock, flags);
440 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
449 spin_lock_irqsave(&sgpio->lock, flags);
451 val = readl(sgpio->chip.regs + offset);
454 writel(val, sgpio->chip.regs + offset);
456 spin_unlock_irqrestore(&sgpio->lock, flags);
462 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
463 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
465 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
471 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
472 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
479 spin_lock_irqsave(&sgpio->lock, flags);
481 val = readl(sgpio->chip.regs + offset);
484 writel(val, sgpio->chip.regs + offset);
486 spin_unlock_irqrestore(&sgpio->lock, flags);
492 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
493 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
500 spin_lock_irqsave(&sgpio->lock, flags);
502 val = readl(sgpio->chip.regs + offset);
535 writel(val, sgpio->chip.regs + offset);
537 spin_unlock_irqrestore(&sgpio->lock, flags);
554 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
562 bank = &sgpio->sgpio_bank[i];
570 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
580 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
600 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
605 val = readl(sgpio->chip.regs + ctrl_offset);
607 writel(val, sgpio->chip.regs + ctrl_offset);
612 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
613 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
625 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
626 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
635 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
636 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
641 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
642 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
651 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
652 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
661 sirfsoc_gpio_set_input(sgpio, offset);
668 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
678 out_ctrl = readl(sgpio->chip.regs + offset);
686 writel(out_ctrl, sgpio->chip.regs + offset);
694 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
695 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
702 spin_lock_irqsave(&sgpio->lock, flags);
704 sirfsoc_gpio_set_output(sgpio, bank, offset, value);
706 spin_unlock_irqrestore(&sgpio->lock, flags);
713 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
714 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
720 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
730 struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
731 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
737 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
742 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
747 static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
756 u32 val = readl(sgpio->chip.regs + offset);
759 writel(val, sgpio->chip.regs + offset);
764 static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
773 u32 val = readl(sgpio->chip.regs + offset);
776 writel(val, sgpio->chip.regs + offset);
784 struct sirfsoc_gpio_chip *sgpio;
796 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
797 if (!sgpio) {
801 spin_lock_init(&sgpio->lock);
809 sgpio->chip.gc.request = sirfsoc_gpio_request;
810 sgpio->chip.gc.free = sirfsoc_gpio_free;
811 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
812 sgpio->chip.gc.get = sirfsoc_gpio_get_value;
813 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
814 sgpio->chip.gc.set = sirfsoc_gpio_set_value;
815 sgpio->chip.gc.base = 0;
816 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
817 sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);
818 sgpio->chip.gc.of_node = np;
819 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
820 sgpio->chip.gc.of_gpio_n_cells = 2;
821 sgpio->chip.gc.parent = &pdev->dev;
822 sgpio->chip.regs = regs;
824 girq = &sgpio->chip.gc.irq;
836 bank = &sgpio->sgpio_bank[i];
848 err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
855 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
865 sirfsoc_gpio_set_pullup(sgpio, pullups);
869 sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
874 gpiochip_remove(&sgpio->chip.gc);