Lines Matching defs:bank
424 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
429 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
441 struct sirfsoc_gpio_bank *bank,
447 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
463 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
465 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
472 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
477 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
493 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
498 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
555 struct sirfsoc_gpio_bank *bank;
562 bank = &sgpio->sgpio_bank[i];
563 if (bank->parent_irq == irq)
570 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
574 __func__, bank->id, status);
580 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
588 __func__, bank->id, idx);
590 bank->id * SIRFSOC_GPIO_BANK_SIZE));
613 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
619 spin_lock_irqsave(&bank->lock, flags);
625 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
626 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
628 spin_unlock_irqrestore(&bank->lock, flags);
636 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
639 spin_lock_irqsave(&bank->lock, flags);
641 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
642 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
644 spin_unlock_irqrestore(&bank->lock, flags);
652 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
657 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
659 spin_lock_irqsave(&bank->lock, flags);
663 spin_unlock_irqrestore(&bank->lock, flags);
669 struct sirfsoc_gpio_bank *bank,
676 spin_lock_irqsave(&bank->lock, flags);
688 spin_unlock_irqrestore(&bank->lock, flags);
695 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
700 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
704 sirfsoc_gpio_set_output(sgpio, bank, offset, value);
714 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
718 spin_lock_irqsave(&bank->lock, flags);
720 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
722 spin_unlock_irqrestore(&bank->lock, flags);
731 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
735 spin_lock_irqsave(&bank->lock, flags);
737 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
742 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
744 spin_unlock_irqrestore(&bank->lock, flags);
785 struct sirfsoc_gpio_bank *bank;
836 bank = &sgpio->sgpio_bank[i];
837 spin_lock_init(&bank->lock);
838 bank->parent_irq = platform_get_irq(pdev, i);
839 if (bank->parent_irq < 0) {
840 err = bank->parent_irq;
843 girq->parents[i] = bank->parent_irq;