Lines Matching refs:bank
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
61 spin_lock_irqsave(&bank->slock, flags);
63 mask = readl(bank->eint_base + reg_mask);
65 writel(mask, bank->eint_base + reg_mask);
67 spin_unlock_irqrestore(&bank->slock, flags);
74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
75 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
77 writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
84 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
85 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
100 spin_lock_irqsave(&bank->slock, flags);
102 mask = readl(bank->eint_base + reg_mask);
104 writel(mask, bank->eint_base + reg_mask);
106 spin_unlock_irqrestore(&bank->slock, flags);
113 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
116 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
144 con = readl(bank->eint_base + reg_con);
147 writel(con, bank->eint_base + reg_con);
154 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
155 const struct samsung_pin_bank_type *bank_type = bank->type;
160 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
162 dev_err(bank->gpio_chip.parent,
164 bank->name, irqd->hwirq);
168 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
172 spin_lock_irqsave(&bank->slock, flags);
174 con = readl(bank->pctl_base + reg_con);
177 writel(con, bank->pctl_base + reg_con);
179 spin_unlock_irqrestore(&bank->slock, flags);
186 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
187 const struct samsung_pin_bank_type *bank_type = bank->type;
191 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
195 spin_lock_irqsave(&bank->slock, flags);
197 con = readl(bank->pctl_base + reg_con);
200 writel(con, bank->pctl_base + reg_con);
202 spin_unlock_irqrestore(&bank->slock, flags);
204 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
248 struct samsung_pin_bank *bank = d->pin_banks;
251 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
257 bank += (group - 1);
259 virq = irq_linear_revmap(bank->irq_domain, pin);
279 struct samsung_pin_bank *bank;
296 bank = d->pin_banks;
297 for (i = 0; i < d->nr_banks; ++i, ++bank) {
298 if (bank->eint_type != EINT_TYPE_GPIO)
301 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
302 sizeof(*bank->irq_chip), GFP_KERNEL);
303 if (!bank->irq_chip) {
307 bank->irq_chip->chip.name = bank->name;
309 bank->irq_domain = irq_domain_add_linear(bank->of_node,
310 bank->nr_pins, &exynos_eint_irqd_ops, bank);
311 if (!bank->irq_domain) {
317 bank->soc_priv = devm_kzalloc(d->dev,
319 if (!bank->soc_priv) {
320 irq_domain_remove(bank->irq_domain);
330 for (--i, --bank; i >= 0; --i, --bank) {
331 if (bank->eint_type != EINT_TYPE_GPIO)
333 irq_domain_remove(bank->irq_domain);
343 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
344 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
364 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
386 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
474 struct samsung_pin_bank *bank = eintd->bank;
480 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
530 struct samsung_pin_bank *bank;
551 bank = d->pin_banks;
552 for (i = 0; i < d->nr_banks; ++i, ++bank) {
553 if (bank->eint_type != EINT_TYPE_WKUP)
556 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
558 if (!bank->irq_chip) {
562 bank->irq_chip->chip.name = bank->name;
564 bank->irq_domain = irq_domain_add_linear(bank->of_node,
565 bank->nr_pins, &exynos_eint_irqd_ops, bank);
566 if (!bank->irq_domain) {
572 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
573 bank->eint_type = EINT_TYPE_WKUP_MUX;
579 bank->nr_pins, sizeof(*weint_data),
586 for (idx = 0; idx < bank->nr_pins; ++idx) {
587 irq = irq_of_parse_and_map(bank->of_node, idx);
590 bank->name, idx);
594 weint_data[idx].bank = bank;
621 bank = d->pin_banks;
623 for (i = 0; i < d->nr_banks; ++i, ++bank) {
624 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
627 muxed_data->banks[idx++] = bank;
636 struct samsung_pin_bank *bank)
638 struct exynos_eint_gpio_save *save = bank->soc_priv;
639 void __iomem *regs = bank->eint_base;
642 + bank->eint_offset);
644 + 2 * bank->eint_offset);
646 + 2 * bank->eint_offset + 4);
647 save->eint_mask = readl(regs + bank->irq_chip->eint_mask
648 + bank->eint_offset);
650 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
651 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
652 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
653 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
658 struct samsung_pin_bank *bank = drvdata->pin_banks;
662 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
663 if (bank->eint_type == EINT_TYPE_GPIO)
664 exynos_pinctrl_suspend_bank(drvdata, bank);
665 else if (bank->eint_type == EINT_TYPE_WKUP) {
667 irq_chip = bank->irq_chip;
677 struct samsung_pin_bank *bank)
679 struct exynos_eint_gpio_save *save = bank->soc_priv;
680 void __iomem *regs = bank->eint_base;
682 pr_debug("%s: con %#010x => %#010x\n", bank->name,
684 + bank->eint_offset), save->eint_con);
685 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
687 + 2 * bank->eint_offset), save->eint_fltcon0);
688 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
690 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
691 pr_debug("%s: mask %#010x => %#010x\n", bank->name,
692 readl(regs + bank->irq_chip->eint_mask
693 + bank->eint_offset), save->eint_mask);
696 + bank->eint_offset);
698 + 2 * bank->eint_offset);
700 + 2 * bank->eint_offset + 4);
701 writel(save->eint_mask, regs + bank->irq_chip->eint_mask
702 + bank->eint_offset);
707 struct samsung_pin_bank *bank = drvdata->pin_banks;
710 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
711 if (bank->eint_type == EINT_TYPE_GPIO)
712 exynos_pinctrl_resume_bank(drvdata, bank);