Lines Matching refs:val
89 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
106 msm_writel_intr_status(val, pctrl, g);
190 u32 val, mask;
220 val = msm_readl_ctl(pctrl, g);
221 val &= ~mask;
222 val |= i << g->mux_bit;
223 msm_writel_ctl(val, pctrl, g);
307 static unsigned msm_regval_to_drive(u32 val)
309 return (val + 1) * 2;
323 u32 val;
331 val = msm_readl_ctl(pctrl, g);
332 arg = (val >> bit) & mask;
376 val = msm_readl_io(pctrl, g);
377 arg = !!(val & BIT(g->in_bit));
407 u32 val;
453 val = msm_readl_io(pctrl, g);
455 val |= BIT(g->out_bit);
457 val &= ~BIT(g->out_bit);
458 msm_writel_io(val, pctrl, g);
481 val = msm_readl_ctl(pctrl, g);
482 val &= ~(mask << bit);
483 val |= arg << bit;
484 msm_writel_ctl(val, pctrl, g);
502 u32 val;
508 val = msm_readl_ctl(pctrl, g);
509 val &= ~BIT(g->oe_bit);
510 msm_writel_ctl(val, pctrl, g);
522 u32 val;
528 val = msm_readl_io(pctrl, g);
530 val |= BIT(g->out_bit);
532 val &= ~BIT(g->out_bit);
533 msm_writel_io(val, pctrl, g);
535 val = msm_readl_ctl(pctrl, g);
536 val |= BIT(g->oe_bit);
537 msm_writel_ctl(val, pctrl, g);
548 u32 val;
552 val = msm_readl_ctl(pctrl, g);
554 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
562 u32 val;
566 val = msm_readl_io(pctrl, g);
567 return !!(val & BIT(g->in_bit));
575 u32 val;
581 val = msm_readl_io(pctrl, g);
583 val |= BIT(g->out_bit);
585 val &= ~BIT(g->out_bit);
586 msm_writel_io(val, pctrl, g);
606 int val;
635 val = !!(io_reg & BIT(g->out_bit));
637 val = !!(io_reg & BIT(g->in_bit));
640 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
749 unsigned val, val2, intstat;
753 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
761 if (intstat || (val == val2))
765 val, val2);
774 u32 val;
786 val = msm_readl_intr_cfg(pctrl, g);
808 val &= ~BIT(g->intr_raw_status_bit);
810 val &= ~BIT(g->intr_enable_bit);
811 msm_writel_intr_cfg(val, pctrl, g);
824 u32 val;
836 val = msm_readl_intr_cfg(pctrl, g);
837 val |= BIT(g->intr_raw_status_bit);
838 val |= BIT(g->intr_enable_bit);
839 msm_writel_intr_cfg(val, pctrl, g);
885 unsigned int val;
889 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
890 type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
897 * Possibly the line changed between when we last read "val"
902 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
904 if (!val)
908 if (val)
959 u32 val;
997 qcom_scm_io_readl(addr, &val);
999 val &= ~(7 << g->intr_target_bit);
1000 val |= g->intr_target_kpss_val << g->intr_target_bit;
1002 ret = qcom_scm_io_writel(addr, val);
1008 val = msm_readl_intr_target(pctrl, g);
1009 val &= ~(7 << g->intr_target_bit);
1010 val |= g->intr_target_kpss_val << g->intr_target_bit;
1011 msm_writel_intr_target(val, pctrl, g);
1019 val = msm_readl_intr_cfg(pctrl, g);
1020 was_enabled = val & BIT(g->intr_raw_status_bit);
1021 val |= BIT(g->intr_raw_status_bit);
1023 val &= ~(3 << g->intr_detection_bit);
1024 val &= ~(1 << g->intr_polarity_bit);
1027 val |= 1 << g->intr_detection_bit;
1028 val |= BIT(g->intr_polarity_bit);
1031 val |= 2 << g->intr_detection_bit;
1032 val |= BIT(g->intr_polarity_bit);
1035 val |= 3 << g->intr_detection_bit;
1036 val |= BIT(g->intr_polarity_bit);
1041 val |= BIT(g->intr_polarity_bit);
1045 val &= ~(1 << g->intr_detection_bit);
1046 val &= ~(1 << g->intr_polarity_bit);
1049 val |= BIT(g->intr_detection_bit);
1050 val |= BIT(g->intr_polarity_bit);
1053 val |= BIT(g->intr_detection_bit);
1056 val |= BIT(g->intr_detection_bit);
1057 val |= BIT(g->intr_polarity_bit);
1062 val |= BIT(g->intr_polarity_bit);
1068 msm_writel_intr_cfg(val, pctrl, g);
1182 u32 val;
1193 val = msm_readl_intr_status(pctrl, g);
1194 if (val & BIT(g->intr_status_bit)) {