Lines Matching defs:pctrl
41 * @pctrl: pinctrl handle.
61 struct pinctrl_dev *pctrl;
84 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
89 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
101 static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
106 msm_writel_intr_status(val, pctrl, g);
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
113 return pctrl->soc->ngroups;
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
121 return pctrl->soc->groups[group].name;
129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
131 *pins = pctrl->soc->groups[group].pins;
132 *num_pins = pctrl->soc->groups[group].npins;
146 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
147 struct gpio_chip *chip = &pctrl->chip;
154 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
156 return pctrl->soc->nfunctions;
162 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
164 return pctrl->soc->functions[function].name;
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
174 *groups = pctrl->soc->functions[function].groups;
175 *num_groups = pctrl->soc->functions[function].ngroups;
183 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
184 struct gpio_chip *gc = &pctrl->chip;
187 unsigned int gpio_func = pctrl->soc->gpio_func;
193 g = &pctrl->soc->groups[group];
215 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
218 raw_spin_lock_irqsave(&pctrl->lock, flags);
220 val = msm_readl_ctl(pctrl, g);
223 msm_writel_ctl(val, pctrl, g);
225 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
228 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
233 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
236 msm_ack_intr_status(pctrl, g);
248 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
249 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
255 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
267 static int msm_config_reg(struct msm_pinctrl *pctrl,
317 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
325 g = &pctrl->soc->groups[group];
327 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
331 val = msm_readl_ctl(pctrl, g);
347 if (pctrl->soc->pull_no_keeper)
355 if (pctrl->soc->pull_no_keeper)
376 val = msm_readl_io(pctrl, g);
400 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
410 g = &pctrl->soc->groups[group];
416 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
429 if (pctrl->soc->pull_no_keeper)
435 if (pctrl->soc->pull_no_keeper)
452 raw_spin_lock_irqsave(&pctrl->lock, flags);
453 val = msm_readl_io(pctrl, g);
458 msm_writel_io(val, pctrl, g);
459 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
469 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
476 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
480 raw_spin_lock_irqsave(&pctrl->lock, flags);
481 val = msm_readl_ctl(pctrl, g);
484 msm_writel_ctl(val, pctrl, g);
485 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
500 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
504 g = &pctrl->soc->groups[offset];
506 raw_spin_lock_irqsave(&pctrl->lock, flags);
508 val = msm_readl_ctl(pctrl, g);
510 msm_writel_ctl(val, pctrl, g);
512 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
520 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
524 g = &pctrl->soc->groups[offset];
526 raw_spin_lock_irqsave(&pctrl->lock, flags);
528 val = msm_readl_io(pctrl, g);
533 msm_writel_io(val, pctrl, g);
535 val = msm_readl_ctl(pctrl, g);
537 msm_writel_ctl(val, pctrl, g);
539 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
546 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
550 g = &pctrl->soc->groups[offset];
552 val = msm_readl_ctl(pctrl, g);
561 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
564 g = &pctrl->soc->groups[offset];
566 val = msm_readl_io(pctrl, g);
573 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
577 g = &pctrl->soc->groups[offset];
579 raw_spin_lock_irqsave(&pctrl->lock, flags);
581 val = msm_readl_io(pctrl, g);
586 msm_writel_io(val, pctrl, g);
588 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
601 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
625 g = &pctrl->soc->groups[offset];
626 ctl_reg = msm_readl_ctl(pctrl, g);
627 io_reg = msm_readl_io(pctrl, g);
642 if (pctrl->soc->pull_no_keeper)
666 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
669 const int *reserved = pctrl->soc->reserved_gpios;
677 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
687 len = ret = device_property_count_u16(pctrl->dev, "gpios");
698 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
700 dev_err(pctrl->dev, "could not read list of GPIOs\n");
744 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
753 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
755 pol = msm_readl_intr_cfg(pctrl, g);
757 msm_writel_intr_cfg(pol, pctrl, g);
759 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
760 intstat = msm_readl_intr_status(pctrl, g);
764 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
771 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
779 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
782 g = &pctrl->soc->groups[d->hwirq];
784 raw_spin_lock_irqsave(&pctrl->lock, flags);
786 val = msm_readl_intr_cfg(pctrl, g);
811 msm_writel_intr_cfg(val, pctrl, g);
813 clear_bit(d->hwirq, pctrl->enabled_irqs);
815 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
821 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
829 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
832 g = &pctrl->soc->groups[d->hwirq];
834 raw_spin_lock_irqsave(&pctrl->lock, flags);
836 val = msm_readl_intr_cfg(pctrl, g);
839 msm_writel_intr_cfg(val, pctrl, g);
841 set_bit(d->hwirq, pctrl->enabled_irqs);
843 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
849 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
854 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
861 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
866 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
882 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
883 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
889 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
902 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
913 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
919 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
923 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
924 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
929 g = &pctrl->soc->groups[d->hwirq];
931 raw_spin_lock_irqsave(&pctrl->lock, flags);
933 msm_ack_intr_status(pctrl, g);
935 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
936 msm_gpio_update_dual_edge_pos(pctrl, g, d);
938 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
945 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
948 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
949 test_bit(d->hwirq, pctrl->skip_wake_irqs);
955 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
962 set_bit(d->hwirq, pctrl->dual_edge_irqs);
971 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
972 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
977 g = &pctrl->soc->groups[d->hwirq];
979 raw_spin_lock_irqsave(&pctrl->lock, flags);
985 set_bit(d->hwirq, pctrl->dual_edge_irqs);
987 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
993 if (pctrl->intr_target_use_scm) {
994 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1004 dev_err(pctrl->dev,
1008 val = msm_readl_intr_target(pctrl, g);
1011 msm_writel_intr_target(val, pctrl, g);
1019 val = msm_readl_intr_cfg(pctrl, g);
1068 msm_writel_intr_cfg(val, pctrl, g);
1076 msm_ack_intr_status(pctrl, g);
1078 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1079 msm_gpio_update_dual_edge_pos(pctrl, g, d);
1081 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1094 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1102 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1105 return irq_set_irq_wake(pctrl->irq, on);
1111 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1117 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1155 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1157 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1166 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1168 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1178 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1191 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1192 g = &pctrl->soc->groups[i];
1193 val = msm_readl_intr_status(pctrl, g);
1214 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1221 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1222 map = &pctrl->soc->wakeirq_map[i];
1232 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1234 if (pctrl->soc->reserved_gpios)
1237 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1240 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1245 unsigned gpio, ngpio = pctrl->soc->ngpios;
1252 chip = &pctrl->chip;
1255 chip->label = dev_name(pctrl->dev);
1256 chip->parent = pctrl->dev;
1258 chip->of_node = pctrl->dev->of_node;
1259 if (msm_gpio_needs_valid_mask(pctrl))
1262 pctrl->irq_chip.name = "msmgpio";
1263 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1264 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1265 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1266 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1267 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1268 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1269 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1270 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1271 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1272 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
1273 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
1274 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND |
1278 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1286 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1292 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1293 gpio = pctrl->soc->wakeirq_map[i].gpio;
1294 set_bit(gpio, pctrl->skip_wake_irqs);
1299 girq->chip = &pctrl->irq_chip;
1301 girq->fwnode = pctrl->dev->fwnode;
1303 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1309 girq->parents[0] = pctrl->irq;
1311 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1313 dev_err(pctrl->dev, "Failed register gpiochip\n");
1327 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1328 ret = gpiochip_add_pin_range(&pctrl->chip,
1329 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1331 dev_err(pctrl->dev, "Failed to add pin range\n");
1332 gpiochip_remove(&pctrl->chip);
1343 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1345 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1357 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1360 const struct msm_function *func = pctrl->soc->functions;
1362 for (i = 0; i < pctrl->soc->nfunctions; i++)
1364 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1365 pctrl->restart_nb.priority = 128;
1366 if (register_restart_handler(&pctrl->restart_nb))
1367 dev_err(pctrl->dev,
1369 poweroff_pctrl = pctrl;
1377 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1379 return pinctrl_force_sleep(pctrl->pctrl);
1384 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1386 return pinctrl_force_default(pctrl->pctrl);
1397 struct msm_pinctrl *pctrl;
1402 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1403 if (!pctrl)
1406 pctrl->dev = &pdev->dev;
1407 pctrl->soc = soc_data;
1408 pctrl->chip = msm_gpio_template;
1409 pctrl->intr_target_use_scm = of_device_is_compatible(
1410 pctrl->dev->of_node,
1413 raw_spin_lock_init(&pctrl->lock);
1419 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1420 if (IS_ERR(pctrl->regs[i]))
1421 return PTR_ERR(pctrl->regs[i]);
1425 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1426 if (IS_ERR(pctrl->regs[0]))
1427 return PTR_ERR(pctrl->regs[0]);
1429 pctrl->phys_base[0] = res->start;
1432 msm_pinctrl_setup_pm_reset(pctrl);
1434 pctrl->irq = platform_get_irq(pdev, 0);
1435 if (pctrl->irq < 0)
1436 return pctrl->irq;
1438 pctrl->desc.owner = THIS_MODULE;
1439 pctrl->desc.pctlops = &msm_pinctrl_ops;
1440 pctrl->desc.pmxops = &msm_pinmux_ops;
1441 pctrl->desc.confops = &msm_pinconf_ops;
1442 pctrl->desc.name = dev_name(&pdev->dev);
1443 pctrl->desc.pins = pctrl->soc->pins;
1444 pctrl->desc.npins = pctrl->soc->npins;
1446 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1447 if (IS_ERR(pctrl->pctrl)) {
1449 return PTR_ERR(pctrl->pctrl);
1452 ret = msm_gpio_init(pctrl);
1456 platform_set_drvdata(pdev, pctrl);
1466 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1468 gpiochip_remove(&pctrl->chip);
1470 unregister_restart_handler(&pctrl->restart_nb);