Lines Matching refs:pcs
210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
273 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
278 if (pcs->bits_per_mux) {
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
288 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
298 struct pcs_device *pcs;
303 pcs = pinctrl_dev_get_drvdata(pctldev);
305 offset = pcs_pin_reg_offset_get(pcs, pin);
306 val = pcs->read(pcs->base + offset);
308 if (pcs->bits_per_mux)
309 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
311 pa = pcs->res->start + offset;
319 struct pcs_device *pcs;
321 pcs = pinctrl_dev_get_drvdata(pctldev);
322 devm_kfree(pcs->dev, map);
341 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
355 dev_err(pcs->dev, "%s could not find function%i\n",
365 struct pcs_device *pcs;
370 pcs = pinctrl_dev_get_drvdata(pctldev);
372 if (!pcs->fmask)
381 dev_dbg(pcs->dev, "enabling %s function%i\n",
390 raw_spin_lock_irqsave(&pcs->lock, flags);
391 val = pcs->read(vals->reg);
393 if (pcs->bits_per_mux)
396 mask = pcs->fmask;
400 pcs->write(val, vals->reg);
401 raw_spin_unlock_irqrestore(&pcs->lock, flags);
410 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
416 if (!pcs->fmask)
419 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
427 offset = pcs_pin_reg_offset_get(pcs, pin);
429 if (pcs->bits_per_mux) {
430 int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
432 data = pcs->read(pcs->base + offset);
433 data &= ~(pcs->fmask << pin_shift);
435 pcs->write(data, pcs->base + offset);
437 data = pcs->read(pcs->base + offset);
438 data &= ~pcs->fmask;
440 pcs->write(data, pcs->base + offset);
488 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
510 offset = pin * (pcs->width / BITS_PER_BYTE);
511 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
552 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
568 offset = pin * (pcs->width / BITS_PER_BYTE);
569 data = pcs->read(pcs->base + offset);
600 pcs->write(data, pcs->base + offset);
680 * @pcs: pcs driver instance
683 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
685 struct pcs_soc_data *pcs_soc = &pcs->socdata;
689 i = pcs->pins.cur;
690 if (i >= pcs->desc.npins) {
691 dev_err(pcs->dev, "too many pins, max %i\n",
692 pcs->desc.npins);
699 val = pcs->read(pcs->base + offset);
701 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
702 (unsigned long)pcs->res->start + offset, val);
704 pcs->write(val, pcs->base + offset);
708 pin = &pcs->pins.pa[i];
710 pcs->pins.cur++;
717 * @pcs: pcs driver instance
724 static int pcs_allocate_pin_table(struct pcs_device *pcs)
729 mux_bytes = pcs->width / BITS_PER_BYTE;
731 if (pcs->bits_per_mux && pcs->fmask) {
732 pcs->bits_per_pin = fls(pcs->fmask);
733 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
734 num_pins_in_register = pcs->width / pcs->bits_per_pin;
736 nr_pins = pcs->size / mux_bytes;
739 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
740 pcs->pins.pa = devm_kcalloc(pcs->dev,
741 nr_pins, sizeof(*pcs->pins.pa),
743 if (!pcs->pins.pa)
746 pcs->desc.pins = pcs->pins.pa;
747 pcs->desc.npins = nr_pins;
749 for (i = 0; i < pcs->desc.npins; i++) {
753 offset = pcs_pin_reg_offset_get(pcs, i);
754 res = pcs_add_pin(pcs, offset);
756 dev_err(pcs->dev, "error adding pins: %i\n", res);
766 * @pcs: pcs driver instance
776 static int pcs_add_function(struct pcs_device *pcs,
787 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
794 selector = pinmux_generic_add_function(pcs->pctl, name,
798 devm_kfree(pcs->dev, function);
809 * @pcs: pcs driver instance
814 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
818 if (offset >= pcs->size) {
819 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
820 offset, pcs->size);
824 if (pcs->bits_per_mux)
825 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
827 index = offset / (pcs->width / BITS_PER_BYTE);
868 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
887 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
899 dev_err(pcs->dev, "mask field of the property can't be 0\n");
907 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
912 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
950 func->conf = devm_kcalloc(pcs->dev,
958 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
965 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
968 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
979 * @pcs: pinctrl driver instance
996 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1009 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1013 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1017 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1031 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1037 vals[found].reg = pcs->base + offset;
1048 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1051 pin = pcs_get_pin_by_offset(pcs, offset);
1053 dev_err(pcs->dev,
1062 mutex_lock(&pcs->mutex);
1063 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1070 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1081 res = pcs_parse_pinconf(pcs, np, function, map);
1091 mutex_unlock(&pcs->mutex);
1096 pinctrl_generic_remove_group(pcs->pctl, gsel);
1099 pinmux_generic_remove_function(pcs->pctl, fsel);
1101 mutex_unlock(&pcs->mutex);
1102 devm_kfree(pcs->dev, pins);
1105 devm_kfree(pcs->dev, vals);
1110 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1124 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1128 npins_in_row = pcs->width / pcs->bits_per_pin;
1130 vals = devm_kzalloc(pcs->dev,
1136 pins = devm_kzalloc(pcs->dev,
1154 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1164 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1170 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1171 mask_pos = ((pcs->fmask) << bit_pos);
1176 dev_err(pcs->dev,
1185 dev_warn(pcs->dev,
1192 vals[found].reg = pcs->base + offset;
1195 pin = pcs_get_pin_by_offset(pcs, offset);
1197 dev_err(pcs->dev,
1207 mutex_lock(&pcs->mutex);
1208 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1215 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1226 dev_err(pcs->dev, "pinconf not supported\n");
1232 mutex_unlock(&pcs->mutex);
1237 pinctrl_generic_remove_group(pcs->pctl, gsel);
1240 pinmux_generic_remove_function(pcs->pctl, fsel);
1242 mutex_unlock(&pcs->mutex);
1243 devm_kfree(pcs->dev, pins);
1246 devm_kfree(pcs->dev, vals);
1261 struct pcs_device *pcs;
1265 pcs = pinctrl_dev_get_drvdata(pctldev);
1268 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1274 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1280 if (pcs->bits_per_mux) {
1281 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1284 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1289 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1292 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1301 devm_kfree(pcs->dev, pgnames);
1303 devm_kfree(pcs->dev, *map);
1310 * @pcs: pcs driver instance
1312 static void pcs_irq_free(struct pcs_device *pcs)
1314 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1319 if (pcs->domain)
1320 irq_domain_remove(pcs->domain);
1330 * @pcs: pcs driver instance
1332 static void pcs_free_resources(struct pcs_device *pcs)
1334 pcs_irq_free(pcs);
1335 pinctrl_unregister(pcs->pctl);
1338 if (pcs->missing_nr_pinctrl_cells)
1339 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1343 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1359 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1367 mutex_lock(&pcs->mutex);
1368 list_add_tail(&range->node, &pcs->gpiofuncs);
1369 mutex_unlock(&pcs->mutex);
1400 struct pcs_device *pcs;
1404 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1405 list_for_each(pos, &pcs->irqs) {
1414 raw_spin_lock(&pcs->lock);
1415 mask = pcs->read(pcswi->reg);
1420 pcs->write(mask, pcswi->reg);
1423 mask = pcs->read(pcswi->reg);
1424 raw_spin_unlock(&pcs->lock);
1481 struct pcs_device *pcs;
1485 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1486 list_for_each(pos, &pcs->irqs) {
1491 raw_spin_lock(&pcs->lock);
1492 mask = pcs->read(pcswi->reg);
1493 raw_spin_unlock(&pcs->lock);
1495 generic_handle_irq(irq_find_mapping(pcs->domain,
1542 struct pcs_device *pcs;
1545 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1546 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1550 pcswi->reg = pcs->base + hwirq;
1554 mutex_lock(&pcs->mutex);
1555 list_add_tail(&pcswi->node, &pcs->irqs);
1556 mutex_unlock(&pcs->mutex);
1559 irq_set_chip_and_handler(irq, &pcs->chip,
1574 * @pcs: pcs driver instance
1577 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1580 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1590 INIT_LIST_HEAD(&pcs->irqs);
1591 pcs->chip.name = name;
1592 pcs->chip.irq_ack = pcs_irq_mask;
1593 pcs->chip.irq_mask = pcs_irq_mask;
1594 pcs->chip.irq_unmask = pcs_irq_unmask;
1595 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1620 num_irqs = pcs->size;
1622 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1625 if (!pcs->domain) {
1634 static int pcs_save_context(struct pcs_device *pcs)
1641 mux_bytes = pcs->width / BITS_PER_BYTE;
1643 if (!pcs->saved_vals) {
1644 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1645 if (!pcs->saved_vals)
1649 switch (pcs->width) {
1651 regsl = pcs->saved_vals;
1652 for (i = 0; i < pcs->size; i += mux_bytes)
1653 *regsl++ = pcs->read(pcs->base + i);
1656 regsw = pcs->saved_vals;
1657 for (i = 0; i < pcs->size; i += mux_bytes)
1658 *regsw++ = pcs->read(pcs->base + i);
1661 regshw = pcs->saved_vals;
1662 for (i = 0; i < pcs->size; i += mux_bytes)
1663 *regshw++ = pcs->read(pcs->base + i);
1670 static void pcs_restore_context(struct pcs_device *pcs)
1677 mux_bytes = pcs->width / BITS_PER_BYTE;
1679 switch (pcs->width) {
1681 regsl = pcs->saved_vals;
1682 for (i = 0; i < pcs->size; i += mux_bytes)
1683 pcs->write(*regsl++, pcs->base + i);
1686 regsw = pcs->saved_vals;
1687 for (i = 0; i < pcs->size; i += mux_bytes)
1688 pcs->write(*regsw++, pcs->base + i);
1691 regshw = pcs->saved_vals;
1692 for (i = 0; i < pcs->size; i += mux_bytes)
1693 pcs->write(*regshw++, pcs->base + i);
1701 struct pcs_device *pcs;
1703 pcs = platform_get_drvdata(pdev);
1704 if (!pcs)
1707 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1710 ret = pcs_save_context(pcs);
1715 return pinctrl_force_sleep(pcs->pctl);
1720 struct pcs_device *pcs;
1722 pcs = platform_get_drvdata(pdev);
1723 if (!pcs)
1726 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1727 pcs_restore_context(pcs);
1729 return pinctrl_force_default(pcs->pctl);
1735 * @pcs: pinctrl driver instance
1743 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1756 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1759 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1764 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1769 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1773 pcs->missing_nr_pinctrl_cells = p;
1776 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1787 struct pcs_device *pcs;
1795 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1796 if (!pcs)
1799 pcs->dev = &pdev->dev;
1800 pcs->np = np;
1801 raw_spin_lock_init(&pcs->lock);
1802 mutex_init(&pcs->mutex);
1803 INIT_LIST_HEAD(&pcs->gpiofuncs);
1804 pcs->flags = soc->flags;
1805 memcpy(&pcs->socdata, soc, sizeof(*soc));
1808 &pcs->width);
1810 dev_err(pcs->dev, "register width not specified\n");
1816 &pcs->fmask);
1818 pcs->fshift = __ffs(pcs->fmask);
1819 pcs->fmax = pcs->fmask >> pcs->fshift;
1822 pcs->fmask = 0;
1823 pcs->fshift = 0;
1824 pcs->fmax = 0;
1828 &pcs->foff);
1830 pcs->foff = PCS_OFF_DISABLED;
1832 pcs->bits_per_mux = of_property_read_bool(np,
1834 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1835 pcs->bits_per_mux ? 2 : 1);
1844 dev_err(pcs->dev, "could not get resource\n");
1848 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1850 if (!pcs->res) {
1851 dev_err(pcs->dev, "could not get mem_region\n");
1855 pcs->size = resource_size(pcs->res);
1856 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1857 if (!pcs->base) {
1858 dev_err(pcs->dev, "could not ioremap\n");
1862 platform_set_drvdata(pdev, pcs);
1864 switch (pcs->width) {
1866 pcs->read = pcs_readb;
1867 pcs->write = pcs_writeb;
1870 pcs->read = pcs_readw;
1871 pcs->write = pcs_writew;
1874 pcs->read = pcs_readl;
1875 pcs->write = pcs_writel;
1881 pcs->desc.name = DRIVER_NAME;
1882 pcs->desc.pctlops = &pcs_pinctrl_ops;
1883 pcs->desc.pmxops = &pcs_pinmux_ops;
1885 pcs->desc.confops = &pcs_pinconf_ops;
1886 pcs->desc.owner = THIS_MODULE;
1888 ret = pcs_allocate_pin_table(pcs);
1892 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1894 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1898 ret = pcs_add_gpio_func(np, pcs);
1902 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1903 if (pcs->socdata.irq)
1904 pcs->flags |= PCS_FEAT_IRQ;
1910 pcs->socdata.rearm = pdata->rearm;
1912 pcs->socdata.irq = pdata->irq;
1913 pcs->flags |= PCS_FEAT_IRQ;
1918 ret = pcs_irq_init_chained_handler(pcs, np);
1920 dev_warn(pcs->dev, "initialized with no interrupts\n");
1923 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1925 return pinctrl_enable(pcs->pctl);
1928 pcs_free_resources(pcs);
1935 struct pcs_device *pcs = platform_get_drvdata(pdev);
1937 if (!pcs)
1940 pcs_free_resources(pcs);