Lines Matching refs:bank
134 * @reg_base: register base of the gpio bank
136 * @clk: clock of the gpio bank
137 * @irq: interrupt of the gpio bank
140 * @nr_pins: number of pins in this bank
141 * @name: name of the bank
142 * @bank_num: number of the bank, to account for holes
143 * @iomux: array describing the 4 iomux sources of the bank
144 * @drv: array describing the 4 drive strength sources of the bank
145 * @pull_type: array describing the 4 pull type sources of the bank
147 * @of_node: dt node of this bank
149 * @domain: irqdomain of the gpio bank
152 * @slock: spinlock for the gpio bank
155 * @route_mask: bits describing the routing pins of per bank
323 * @num: bank number.
345 * @bank_num: bank number.
376 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
379 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
382 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
455 * given a pin number that is local to a pin controller, find out the pin bank
456 * and the register base of the pin bank.
823 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
826 struct rockchip_pinctrl *info = bank->drvdata;
833 if (data->num == bank->bank_num &&
1046 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1049 struct rockchip_pinctrl *info = bank->drvdata;
1056 if ((data->bank_num == bank->bank_num) &&
1071 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1073 struct rockchip_pinctrl *info = bank->drvdata;
1083 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1088 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1091 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1095 mux_type = bank->iomux[iomux_num].type;
1096 reg = bank->iomux[iomux_num].offset;
1112 if (bank->recalced_mask & BIT(pin))
1113 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1122 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1125 struct rockchip_pinctrl *info = bank->drvdata;
1131 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1136 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1156 * @bank: pin bank to change
1160 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1162 struct rockchip_pinctrl *info = bank->drvdata;
1169 ret = rockchip_verify_mux(bank, pin, mux);
1173 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1177 bank->bank_num, pin, mux);
1179 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1183 mux_type = bank->iomux[iomux_num].type;
1184 reg = bank->iomux[iomux_num].offset;
1200 if (bank->recalced_mask & BIT(pin))
1201 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1203 if (bank->route_mask & BIT(pin)) {
1204 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1238 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1242 struct rockchip_pinctrl *info = bank->drvdata;
1244 /* The first 32 pins of the first bank are located in PMU */
1245 if (bank->bank_num == 0) {
1252 /* correct the offset, as we're starting with the 2nd bank */
1254 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1268 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1272 struct rockchip_pinctrl *info = bank->drvdata;
1274 /* The first 32 pins of the first bank are located in PMU */
1275 if (bank->bank_num == 0) {
1282 /* correct the offset, as we're starting with the 2nd bank */
1284 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1298 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1303 struct rockchip_pinctrl *info = bank->drvdata;
1306 if (bank->bank_num == 0) {
1314 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1329 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1333 struct rockchip_pinctrl *info = bank->drvdata;
1335 /* The first 24 pins of the first bank are located in PMU */
1336 if (bank->bank_num == 0) {
1342 /* correct the offset, as we're starting with the 2nd bank */
1344 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1358 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1362 struct rockchip_pinctrl *info = bank->drvdata;
1364 /* The first 24 pins of the first bank are located in PMU */
1365 if (bank->bank_num == 0) {
1372 /* correct the offset, as we're starting with the 2nd bank */
1374 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1388 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1393 struct rockchip_pinctrl *info = bank->drvdata;
1396 if (bank->bank_num == 0) {
1404 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1416 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1420 struct rockchip_pinctrl *info = bank->drvdata;
1425 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1436 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1440 struct rockchip_pinctrl *info = bank->drvdata;
1444 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1452 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1456 struct rockchip_pinctrl *info = bank->drvdata;
1460 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1472 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1476 struct rockchip_pinctrl *info = bank->drvdata;
1478 /* The first 12 pins of the first bank are located elsewhere */
1479 if (bank->bank_num == 0 && pin_num < 12) {
1481 : bank->regmap_pull;
1493 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1507 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1511 struct rockchip_pinctrl *info = bank->drvdata;
1513 /* The first 24 pins of the first bank are located in PMU */
1514 if (bank->bank_num == 0) {
1525 /* correct the offset, as we're starting with the 2nd bank */
1527 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1541 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1545 struct rockchip_pinctrl *info = bank->drvdata;
1547 /* The first 24 pins of the first bank are located in PMU */
1548 if (bank->bank_num == 0) {
1559 /* correct the offset, as we're starting with the 2nd bank */
1561 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1571 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1575 struct rockchip_pinctrl *info = bank->drvdata;
1579 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1588 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1592 struct rockchip_pinctrl *info = bank->drvdata;
1596 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1605 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1609 struct rockchip_pinctrl *info = bank->drvdata;
1613 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1622 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1626 struct rockchip_pinctrl *info = bank->drvdata;
1630 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1640 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1644 struct rockchip_pinctrl *info = bank->drvdata;
1646 /* The first 32 pins of the first bank are located in PMU */
1647 if (bank->bank_num == 0) {
1658 /* correct the offset, as we're starting with the 2nd bank */
1660 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1671 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1675 struct rockchip_pinctrl *info = bank->drvdata;
1677 /* The first 32 pins of the first bank are located in PMU */
1678 if (bank->bank_num == 0) {
1689 /* correct the offset, as we're starting with the 2nd bank */
1691 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1703 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1707 struct rockchip_pinctrl *info = bank->drvdata;
1710 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1714 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1723 /* correct the offset, as we're starting with the 3rd bank */
1725 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1733 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1737 struct rockchip_pinctrl *info = bank->drvdata;
1741 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1746 *reg = bank->drv[drv_num].offset;
1747 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1748 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1760 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1764 struct rockchip_pinctrl *info = bank->drvdata;
1766 if (bank->bank_num == 0) {
1769 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1777 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1791 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1795 struct rockchip_pinctrl *info = bank->drvdata;
1797 /* The first 32 pins of the first bank are located in PMU */
1798 if (bank->bank_num == 0) {
1808 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
1824 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1827 struct rockchip_pinctrl *info = bank->drvdata;
1833 int drv_type = bank->drv[pin_num / 8].drv_type;
1835 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1901 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1904 struct rockchip_pinctrl *info = bank->drvdata;
1910 int drv_type = bank->drv[pin_num / 8].drv_type;
1913 bank->bank_num, pin_num, strength);
1915 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2016 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2018 struct rockchip_pinctrl *info = bank->drvdata;
2029 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2049 pull_type = bank->pull_type[pin_num / 8];
2056 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2068 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2071 struct rockchip_pinctrl *info = bank->drvdata;
2079 bank->bank_num, pin_num, pull);
2085 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2103 pull_type = bank->pull_type[pin_num / 8];
2116 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2147 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2152 struct rockchip_pinctrl *info = bank->drvdata;
2157 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2170 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2175 struct rockchip_pinctrl *info = bank->drvdata;
2177 if (bank->bank_num == 0) {
2183 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2193 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2195 struct rockchip_pinctrl *info = bank->drvdata;
2202 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2221 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2224 struct rockchip_pinctrl *info = bank->drvdata;
2232 bank->bank_num, pin_num, enable);
2234 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2291 struct rockchip_pin_bank *bank;
2302 bank = pin_to_bank(info, pins[cnt]);
2303 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2312 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2322 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2326 ret = clk_enable(bank->clk);
2328 dev_err(bank->drvdata->dev,
2329 "failed to enable clock for bank %s\n", bank->name);
2332 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2333 clk_disable(bank->clk);
2349 struct rockchip_pin_bank *bank;
2354 bank = gpiochip_get_data(chip);
2356 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2360 clk_enable(bank->clk);
2361 raw_spin_lock_irqsave(&bank->slock, flags);
2363 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2369 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2371 raw_spin_unlock_irqrestore(&bank->slock, flags);
2372 clk_disable(bank->clk);
2438 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2450 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2465 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2471 rockchip_gpio_set(&bank->gpio_chip,
2472 pin - bank->pin_base, arg);
2473 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2474 pin - bank->pin_base, false);
2483 rc = rockchip_set_drive_perpin(bank,
2484 pin - bank->pin_base, arg);
2492 rc = rockchip_set_schmitt(bank,
2493 pin - bank->pin_base, arg);
2511 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2518 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2530 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2536 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2540 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2551 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2561 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2584 { .compatible = "rockchip,gpio-bank" },
2608 struct rockchip_pin_bank *bank;
2621 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2648 bank = bank_num_to_bank(info, num);
2649 if (IS_ERR(bank))
2650 return PTR_ERR(bank);
2652 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2760 int pin, bank, ret;
2779 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2780 pin_bank = &info->ctrl->pin_banks[bank];
2799 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2800 pin_bank = &info->ctrl->pin_banks[bank];
2802 pin_bank->grange.id = bank;
2819 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2820 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2824 clk_enable(bank->clk);
2825 raw_spin_lock_irqsave(&bank->slock, flags);
2833 raw_spin_unlock_irqrestore(&bank->slock, flags);
2834 clk_disable(bank->clk);
2843 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2846 clk_enable(bank->clk);
2847 data = readl(bank->reg_base + GPIO_EXT_PORT);
2848 clk_disable(bank->clk);
2879 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2880 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2884 clk_enable(bank->clk);
2885 raw_spin_lock_irqsave(&bank->slock, flags);
2894 raw_spin_unlock_irqrestore(&bank->slock, flags);
2895 clk_disable(bank->clk);
2934 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2937 if (!bank->domain)
2940 clk_enable(bank->clk);
2941 virq = irq_create_mapping(bank->domain, offset);
2942 clk_disable(bank->clk);
2967 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2970 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2974 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2981 virq = irq_find_mapping(bank->domain, irq);
2984 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2988 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2994 if (bank->toggle_edge_mode & BIT(irq)) {
2998 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
3000 raw_spin_lock_irqsave(&bank->slock, flags);
3002 polarity = readl_relaxed(bank->reg_base +
3009 bank->reg_base + GPIO_INT_POLARITY);
3011 raw_spin_unlock_irqrestore(&bank->slock, flags);
3014 data = readl_relaxed(bank->reg_base +
3028 struct rockchip_pin_bank *bank = gc->private;
3037 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3041 clk_enable(bank->clk);
3042 raw_spin_lock_irqsave(&bank->slock, flags);
3044 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3046 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3048 raw_spin_unlock_irqrestore(&bank->slock, flags);
3055 raw_spin_lock_irqsave(&bank->slock, flags);
3063 bank->toggle_edge_mode |= mask;
3070 data = readl(bank->reg_base + GPIO_EXT_PORT);
3077 bank->toggle_edge_mode &= ~mask;
3082 bank->toggle_edge_mode &= ~mask;
3087 bank->toggle_edge_mode &= ~mask;
3092 bank->toggle_edge_mode &= ~mask;
3098 raw_spin_unlock_irqrestore(&bank->slock, flags);
3099 clk_disable(bank->clk);
3107 raw_spin_unlock_irqrestore(&bank->slock, flags);
3108 clk_disable(bank->clk);
3116 struct rockchip_pin_bank *bank = gc->private;
3118 clk_enable(bank->clk);
3119 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3121 clk_disable(bank->clk);
3127 struct rockchip_pin_bank *bank = gc->private;
3129 clk_enable(bank->clk);
3130 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3131 clk_disable(bank->clk);
3137 struct rockchip_pin_bank *bank = gc->private;
3139 clk_enable(bank->clk);
3146 struct rockchip_pin_bank *bank = gc->private;
3149 clk_disable(bank->clk);
3156 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3162 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3163 if (!bank->valid) {
3164 dev_warn(&pdev->dev, "bank %s is not valid\n",
3165 bank->name);
3169 ret = clk_enable(bank->clk);
3171 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3172 bank->name);
3176 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3178 if (!bank->domain) {
3179 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3180 bank->name);
3181 clk_disable(bank->clk);
3185 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3189 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3190 bank->name);
3191 irq_domain_remove(bank->domain);
3192 clk_disable(bank->clk);
3196 gc = irq_get_domain_generic_chip(bank->domain, 0);
3197 gc->reg_base = bank->reg_base;
3198 gc->private = bank;
3210 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3217 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3218 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3221 irq_set_chained_handler_and_data(bank->irq,
3222 rockchip_irq_demux, bank);
3223 clk_disable(bank->clk);
3233 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3238 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3239 if (!bank->valid) {
3240 dev_warn(&pdev->dev, "bank %s is not valid\n",
3241 bank->name);
3245 bank->gpio_chip = rockchip_gpiolib_chip;
3247 gc = &bank->gpio_chip;
3248 gc->base = bank->pin_base;
3249 gc->ngpio = bank->nr_pins;
3251 gc->of_node = bank->of_node;
3252 gc->label = bank->name;
3254 ret = gpiochip_add_data(gc, bank);
3267 for (--i, --bank; i >= 0; --i, --bank) {
3268 if (!bank->valid)
3270 gpiochip_remove(&bank->gpio_chip);
3279 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3282 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3283 if (!bank->valid)
3285 gpiochip_remove(&bank->gpio_chip);
3291 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3297 if (of_address_to_resource(bank->of_node, 0, &res)) {
3298 dev_err(info->dev, "cannot find IO resource for bank\n");
3302 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3303 if (IS_ERR(bank->reg_base))
3304 return PTR_ERR(bank->reg_base);
3310 if (of_device_is_compatible(bank->of_node,
3314 node = of_parse_phandle(bank->of_node->parent,
3317 if (of_address_to_resource(bank->of_node, 1, &res)) {
3318 dev_err(info->dev, "cannot find IO resource for bank\n");
3329 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3336 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3338 bank->clk = of_clk_get(bank->of_node, 0);
3339 if (IS_ERR(bank->clk))
3340 return PTR_ERR(bank->clk);
3342 return clk_prepare(bank->clk);
3356 struct rockchip_pin_bank *bank;
3366 bank = ctrl->pin_banks;
3367 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3368 if (!strcmp(bank->name, np->name)) {
3369 bank->of_node = np;
3371 if (!rockchip_get_bank_data(bank, d))
3372 bank->valid = true;
3383 bank = ctrl->pin_banks;
3384 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3387 raw_spin_lock_init(&bank->slock);
3388 bank->drvdata = d;
3389 bank->pin_base = ctrl->nr_pins;
3390 ctrl->nr_pins += bank->nr_pins;
3394 struct rockchip_iomux *iom = &bank->iomux[j];
3395 struct rockchip_drv *drv = &bank->drv[j];
3398 if (bank_pins >= bank->nr_pins)
3423 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3456 /* calculate the per-bank recalced_mask */
3460 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3462 bank->recalced_mask |= BIT(pin);
3466 /* calculate the per-bank route_mask */
3470 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3472 bank->route_mask |= BIT(pin);