Lines Matching refs:val
836 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
838 writel(val, pctl->base + reg);
851 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
854 writel(val, bank->base + reg);
858 u32 reg, unsigned int bit, u32 val)
864 gpio_writel(bank, (0x10000 | val) << bit, reg);
951 u32 val;
964 val = pctl_readl(pctl, pg->mux_reg);
965 val &= ~(pg->mux_mask << pg->mux_shift);
966 val |= i << pg->mux_shift;
967 pctl_writel(pctl, val, pg->mux_reg);
977 val = pctl_readl(pctl, pf->scenario_reg);
978 val &= ~(pf->scenario_mask << pf->scenario_shift);
979 val |= i << pf->scenario_shift;
980 pctl_writel(pctl, val, pf->scenario_reg);
1003 u32 val, arg;
1007 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1008 arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
1011 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1013 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
1016 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1018 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
1021 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1023 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
1026 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1028 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
1031 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1032 arg = !!(val & PADS_SLEW_RATE_BIT(pin));
1035 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1037 switch (val & PADS_DRIVE_STRENGTH_MASK) {
1068 u32 drv, val, arg;
1077 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1079 val |= PADS_SCHMITT_EN_BIT(pin);
1081 val &= ~PADS_SCHMITT_EN_BIT(pin);
1082 pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1085 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1086 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1087 val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
1088 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1091 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1092 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1093 val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
1094 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1097 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1098 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1099 val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
1100 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1103 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1104 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1105 val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
1106 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1109 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1111 val |= PADS_SLEW_RATE_BIT(pin);
1113 val &= ~PADS_SLEW_RATE_BIT(pin);
1114 pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1117 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1118 val &= ~(PADS_DRIVE_STRENGTH_MASK <<
1139 val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
1140 pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));