Lines Matching defs:pctl
94 struct pistachio_pinctrl *pctl;
831 static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
833 return readl(pctl->base + reg);
836 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
838 writel(val, pctl->base + reg);
881 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
883 return pctl->ngroups;
889 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
891 return pctl->groups[group].name;
899 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
901 *pins = &pctl->groups[group].pin;
917 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
919 return pctl->nfunctions;
925 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
927 return pctl->functions[func].name;
935 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
937 *groups = pctl->functions[func].groups;
938 *num_groups = pctl->functions[func].ngroups;
946 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
947 const struct pistachio_pin_group *pg = &pctl->groups[group];
948 const struct pistachio_function *pf = &pctl->functions[func];
959 dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
964 val = pctl_readl(pctl, pg->mux_reg);
967 pctl_writel(pctl, val, pg->mux_reg);
977 val = pctl_readl(pctl, pf->scenario_reg);
980 pctl_writel(pctl, val, pf->scenario_reg);
984 range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
1001 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1007 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1011 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1016 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1021 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1026 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1031 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1035 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1054 dev_dbg(pctl->dev, "Property %u not supported\n", param);
1066 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1077 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1082 pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1085 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1088 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1091 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1094 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1097 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1100 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1103 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1106 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1109 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1114 pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1117 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1134 dev_err(pctl->dev,
1140 pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
1143 dev_err(pctl->dev, "Property %u not supported\n",
1348 static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1350 struct device_node *node = pctl->dev->of_node;
1355 for (i = 0; i < pctl->nbanks; i++) {
1363 dev_err(pctl->dev, "No node for bank %u\n", i);
1369 dev_err(pctl->dev,
1378 dev_err(pctl->dev, "No IRQ for bank %u\n", i);
1384 bank = &pctl->gpio_banks[i];
1385 bank->pctl = pctl;
1386 bank->base = pctl->base + GPIO_BANK_BASE(i);
1388 bank->gpio_chip.parent = pctl->dev;
1395 girq->parents = devm_kcalloc(pctl->dev, 1,
1408 dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1414 dev_name(pctl->dev), 0,
1417 dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
1427 bank = &pctl->gpio_banks[i - 1];
1440 struct pistachio_pinctrl *pctl;
1442 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1443 if (!pctl)
1445 pctl->dev = &pdev->dev;
1446 dev_set_drvdata(&pdev->dev, pctl);
1448 pctl->base = devm_platform_ioremap_resource(pdev, 0);
1449 if (IS_ERR(pctl->base))
1450 return PTR_ERR(pctl->base);
1452 pctl->pins = pistachio_pins;
1453 pctl->npins = ARRAY_SIZE(pistachio_pins);
1454 pctl->functions = pistachio_functions;
1455 pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
1456 pctl->groups = pistachio_groups;
1457 pctl->ngroups = ARRAY_SIZE(pistachio_groups);
1458 pctl->gpio_banks = pistachio_gpio_banks;
1459 pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
1461 pistachio_pinctrl_desc.pins = pctl->pins;
1462 pistachio_pinctrl_desc.npins = pctl->npins;
1464 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
1465 pctl);
1466 if (IS_ERR(pctl->pctldev)) {
1468 return PTR_ERR(pctl->pctldev);
1471 return pistachio_gpio_register(pctl);