Lines Matching refs:mcp
136 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
138 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
141 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
143 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
146 static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
150 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
154 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
158 return mcp_set_mask(mcp, reg, mask, enabled);
223 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
230 ret = mcp_read(mcp, MCP_GPPU, &data);
247 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
259 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
262 dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
280 struct mcp23s08 *mcp = gpiochip_get_data(chip);
283 mutex_lock(&mcp->lock);
284 status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
285 mutex_unlock(&mcp->lock);
292 struct mcp23s08 *mcp = gpiochip_get_data(chip);
295 mutex_lock(&mcp->lock);
298 ret = mcp_read(mcp, MCP_GPIO, &status);
302 mcp->cached_gpio = status;
306 mutex_unlock(&mcp->lock);
310 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
312 return mcp_set_mask(mcp, MCP_OLAT, mask, value);
317 struct mcp23s08 *mcp = gpiochip_get_data(chip);
320 mutex_lock(&mcp->lock);
321 __mcp23s08_set(mcp, mask, !!value);
322 mutex_unlock(&mcp->lock);
328 struct mcp23s08 *mcp = gpiochip_get_data(chip);
332 mutex_lock(&mcp->lock);
333 status = __mcp23s08_set(mcp, mask, value);
335 status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
337 mutex_unlock(&mcp->lock);
344 struct mcp23s08 *mcp = data;
350 mutex_lock(&mcp->lock);
351 if (mcp_read(mcp, MCP_INTF, &intf))
359 if (mcp_read(mcp, MCP_INTCAP, &intcap))
362 if (mcp_read(mcp, MCP_INTCON, &intcon))
365 if (mcp_read(mcp, MCP_DEFVAL, &defval))
369 if (mcp_read(mcp, MCP_GPIO, &gpio))
372 gpio_orig = mcp->cached_gpio;
373 mcp->cached_gpio = gpio;
374 mutex_unlock(&mcp->lock);
376 dev_dbg(mcp->chip.parent,
380 for (i = 0; i < mcp->chip.ngpio; i++) {
418 (BIT(i) & mcp->irq_rise) && gpio_set) ||
420 (BIT(i) & mcp->irq_fall) && !gpio_set) ||
422 child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
430 mutex_unlock(&mcp->lock);
437 struct mcp23s08 *mcp = gpiochip_get_data(gc);
440 mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
446 struct mcp23s08 *mcp = gpiochip_get_data(gc);
449 mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
455 struct mcp23s08 *mcp = gpiochip_get_data(gc);
459 mcp_set_bit(mcp, MCP_INTCON, pos, false);
460 mcp->irq_rise |= BIT(pos);
461 mcp->irq_fall |= BIT(pos);
463 mcp_set_bit(mcp, MCP_INTCON, pos, false);
464 mcp->irq_rise |= BIT(pos);
465 mcp->irq_fall &= ~BIT(pos);
467 mcp_set_bit(mcp, MCP_INTCON, pos, false);
468 mcp->irq_rise &= ~BIT(pos);
469 mcp->irq_fall |= BIT(pos);
471 mcp_set_bit(mcp, MCP_INTCON, pos, true);
472 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
474 mcp_set_bit(mcp, MCP_INTCON, pos, true);
475 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
485 struct mcp23s08 *mcp = gpiochip_get_data(gc);
487 mutex_lock(&mcp->lock);
488 regcache_cache_only(mcp->regmap, true);
494 struct mcp23s08 *mcp = gpiochip_get_data(gc);
496 regcache_cache_only(mcp->regmap, false);
497 regcache_sync(mcp->regmap);
499 mutex_unlock(&mcp->lock);
502 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
504 struct gpio_chip *chip = &mcp->chip;
508 if (mcp->irq_active_high)
513 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
515 irqflags, dev_name(chip->parent), mcp);
518 mcp->irq, err);
527 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
534 mutex_init(&mcp->lock);
536 mcp->dev = dev;
537 mcp->addr = addr;
539 mcp->irq_active_high = false;
540 mcp->irq_chip.name = dev_name(dev);
541 mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
542 mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
543 mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
544 mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
545 mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
547 mcp->chip.direction_input = mcp23s08_direction_input;
548 mcp->chip.get = mcp23s08_get;
549 mcp->chip.direction_output = mcp23s08_direction_output;
550 mcp->chip.set = mcp23s08_set;
552 mcp->chip.of_gpio_n_cells = 2;
553 mcp->chip.of_node = dev->of_node;
556 mcp->chip.base = base;
557 mcp->chip.can_sleep = true;
558 mcp->chip.parent = dev;
559 mcp->chip.owner = THIS_MODULE;
565 ret = mcp_read(mcp, MCP_IOCON, &status);
569 mcp->irq_controller =
571 if (mcp->irq && mcp->irq_controller) {
572 mcp->irq_active_high =
581 mcp->irq_active_high || open_drain) {
585 if (mcp->irq_active_high)
599 ret = mcp_write(mcp, MCP_IOCON, status);
604 if (mcp->irq && mcp->irq_controller) {
605 struct gpio_irq_chip *girq = &mcp->chip.irq;
607 girq->chip = &mcp->irq_chip;
617 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
621 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
622 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
623 mcp->pinctrl_desc.npins = mcp->chip.ngpio;
624 if (mcp->pinctrl_desc.npins == 8)
625 mcp->pinctrl_desc.pins = mcp23x08_pins;
626 else if (mcp->pinctrl_desc.npins == 16)
627 mcp->pinctrl_desc.pins = mcp23x17_pins;
628 mcp->pinctrl_desc.owner = THIS_MODULE;
630 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
631 if (IS_ERR(mcp->pctldev))
632 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
634 if (mcp->irq) {
635 ret = mcp23s08_irq_setup(mcp);