Lines Matching defs:jzgc
2006 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
2010 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
2015 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
2023 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
2026 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
2034 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
2035 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
2038 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
2040 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
2041 jzgc->jzpc->info->reg_offset),
2042 jzgc->gc.base / PINS_PER_GPIO_CHIP);
2045 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
2048 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
2053 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
2056 if (jzgc->jzpc->info->version >= ID_JZ4770)
2057 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
2059 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
2062 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
2086 if (jzgc->jzpc->info->version >= ID_JZ4770) {
2094 if (jzgc->jzpc->info->version >= ID_X1000) {
2095 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
2096 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
2097 ingenic_gpio_shadow_set_bit_load(jzgc);
2099 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
2100 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
2107 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2109 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
2115 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2117 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
2123 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2126 if (jzgc->jzpc->info->version >= ID_JZ4770)
2127 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
2129 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
2137 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2142 if (jzgc->jzpc->info->version >= ID_JZ4770)
2143 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
2145 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
2151 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2160 high = ingenic_gpio_get_value(jzgc, irq);
2162 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
2164 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
2167 if (jzgc->jzpc->info->version >= ID_JZ4770)
2168 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
2170 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
2176 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2198 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
2203 irq_set_type(jzgc, irqd->hwirq, type);
2210 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2212 return irq_set_irq_wake(jzgc->irq, on);
2218 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2224 if (jzgc->jzpc->info->version >= ID_JZ4770)
2225 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
2227 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
2237 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2239 ingenic_gpio_set_value(jzgc, offset, value);
2244 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2246 return (int) ingenic_gpio_get_value(jzgc, offset);
2302 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2303 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
2657 struct ingenic_gpio_chip *jzgc;
2669 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
2670 if (!jzgc)
2673 jzgc->jzpc = jzpc;
2674 jzgc->reg_base = bank * jzpc->info->reg_offset;
2676 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
2677 if (!jzgc->gc.label)
2684 jzgc->gc.base = bank * 32;
2686 jzgc->gc.ngpio = 32;
2687 jzgc->gc.parent = dev;
2688 jzgc->gc.of_node = node;
2689 jzgc->gc.owner = THIS_MODULE;
2691 jzgc->gc.set = ingenic_gpio_set;
2692 jzgc->gc.get = ingenic_gpio_get;
2693 jzgc->gc.direction_input = ingenic_gpio_direction_input;
2694 jzgc->gc.direction_output = ingenic_gpio_direction_output;
2695 jzgc->gc.get_direction = ingenic_gpio_get_direction;
2696 jzgc->gc.request = gpiochip_generic_request;
2697 jzgc->gc.free = gpiochip_generic_free;
2699 jzgc->irq = irq_of_parse_and_map(node, 0);
2700 if (!jzgc->irq)
2703 jzgc->irq_chip.name = jzgc->gc.label;
2704 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
2705 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
2706 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
2707 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
2708 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
2709 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
2710 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
2711 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
2712 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
2713 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2715 girq = &jzgc->gc.irq;
2716 girq->chip = &jzgc->irq_chip;
2723 girq->parents[0] = jzgc->irq;
2727 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);