Lines Matching defs:gctrl
27 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
31 raw_spin_lock_irqsave(&gctrl->lock, flags);
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
39 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
44 raw_spin_lock_irqsave(&gctrl->lock, flags);
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
46 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
52 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
56 raw_spin_lock_irqsave(&gctrl->lock, flags);
57 writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
58 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
77 struct eqbr_gpio_ctrl *gctrl,
82 raw_spin_lock_irqsave(&gctrl->lock, flags);
83 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);
84 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);
85 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);
86 raw_spin_unlock_irqrestore(&gctrl->lock, flags);
94 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
138 eqbr_irq_type_cfg(&it, gctrl, offset);
150 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
155 pins = readl(gctrl->membase + GPIO_IRNCR);
163 static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
168 gc = &gctrl->chip;
169 gc->label = gctrl->name;
171 gc->of_node = gctrl->node;
174 if (!of_property_read_bool(gctrl->node, "interrupt-controller")) {
176 gctrl->name);
180 gctrl->ic.name = "gpio_irq";
181 gctrl->ic.irq_mask = eqbr_gpio_disable_irq;
182 gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;
183 gctrl->ic.irq_ack = eqbr_gpio_ack_irq;
184 gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;
185 gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;
187 girq = &gctrl->chip.irq;
188 girq->chip = &gctrl->ic;
197 girq->parents[0] = gctrl->virq;
205 struct eqbr_gpio_ctrl *gctrl;
211 gctrl = drvdata->gpio_ctrls + i;
212 np = gctrl->node;
214 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
215 if (!gctrl->name)
223 gctrl->membase = devm_ioremap_resource(dev, &res);
224 if (IS_ERR(gctrl->membase))
225 return PTR_ERR(gctrl->membase);
227 gctrl->virq = irq_of_parse_and_map(np, 0);
228 if (!gctrl->virq) {
230 gctrl->name);
233 raw_spin_lock_init(&gctrl->lock);
235 ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
236 gctrl->membase + GPIO_IN,
237 gctrl->membase + GPIO_OUTSET,
238 gctrl->membase + GPIO_OUTCLR,
239 gctrl->membase + GPIO_DIR,
246 ret = gpiochip_setup(dev, gctrl);
250 ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);
380 struct eqbr_gpio_ctrl *gctrl;
420 gctrl = get_gpio_ctrls_via_bank(pctl, bank);
421 if (!gctrl) {
427 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));
443 struct eqbr_gpio_ctrl *gctrl;
489 gctrl = get_gpio_ctrls_via_bank(pctl, bank);
490 if (!gctrl) {
495 gc = &gctrl->chip;