Lines Matching refs:pins
26 #define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
59 struct pinctrl_pin_desc *pins;
69 const unsigned int *pins;
80 /* pins */
215 .pins = cpuclkout_pins0,
221 .pins = udlclkout_pins0,
227 .pins = i2c1_pins0,
233 .pins = i2c2_pins0,
239 .pins = i2c3_pins0,
245 .pins = i2s0_pins0,
251 .pins = i2s1_pins0,
257 .pins = i2srefclk_pins0,
263 .pins = spi0_pins0,
269 .pins = spi1_pins0,
275 .pins = pciedebug_pins0,
280 .name = "uart0grp0", /* All pins. */
281 .pins = uart0_pins0,
287 .pins = uart0_pins1,
292 .name = "uart0grp2", /* Only RX/TX pins. */
293 .pins = uart0_pins1,
299 .pins = uart1_pins0,
304 .name = "uart1grp1", /* Only RX/TX pins. */
305 .pins = uart1_pins0,
311 .pins = uart2_pins0,
317 .pins = uart2_pins1,
323 .pins = uart2_pins1,
329 .pins = uart3_pins0,
335 .pins = uart3_pins0,
341 .pins = uart4_pins0,
347 .pins = uart5_pins0,
353 .pins = uart5_pins0,
359 .pins = uart5_pins0,
365 .pins = nand_pins0,
371 .pins = sdio0_pins0,
377 .pins = sdio1_pins0,
383 .pins = ethernet_pins0,
437 const unsigned int **pins,
440 *pins = (unsigned int *)artpec6_pin_groups[group].pins;
664 * Registers for pins above a ARTPEC6_MAX_MUXABLE
667 if (artpec6_pin_groups[group].pins[i] > ARTPEC6_MAX_MUXABLE)
682 reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]);
743 pmx->pins[pin].name);
748 pmx->pins[pin].name);
807 pmx->pins[pin].name);
812 pmx->pins[pin].name);
893 artpec6_pin_groups[group].pins[current_pin],
913 .pins = artpec6_pins,
953 pmx->pins = artpec6_pins;