Lines Matching defs:pin_reg
42 u32 pin_reg;
46 pin_reg = readl(gpio_dev->base + offset * 4);
49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
58 u32 pin_reg;
62 pin_reg = readl(gpio_dev->base + offset * 4);
63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64 writel(pin_reg, gpio_dev->base + offset * 4);
73 u32 pin_reg;
78 pin_reg = readl(gpio_dev->base + offset * 4);
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
81 pin_reg |= BIT(OUTPUT_VALUE_OFF);
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84 writel(pin_reg, gpio_dev->base + offset * 4);
92 u32 pin_reg;
97 pin_reg = readl(gpio_dev->base + offset * 4);
100 return !!(pin_reg & BIT(PIN_STS_OFF));
105 u32 pin_reg;
110 pin_reg = readl(gpio_dev->base + offset * 4);
112 pin_reg |= BIT(OUTPUT_VALUE_OFF);
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115 writel(pin_reg, gpio_dev->base + offset * 4);
123 u32 pin_reg;
132 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
133 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
137 pin_reg = readl(gpio_dev->base + offset * 4);
140 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
141 pin_reg &= ~DB_TMR_OUT_MASK;
153 pin_reg |= 1;
154 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
155 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg |= time & DB_TMR_OUT_MASK;
159 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
160 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
163 pin_reg |= time & DB_TMR_OUT_MASK;
164 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
165 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
168 pin_reg |= time & DB_TMR_OUT_MASK;
169 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
170 pin_reg |= BIT(DB_TMR_LARGE_OFF);
173 pin_reg |= time & DB_TMR_OUT_MASK;
174 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
175 pin_reg |= BIT(DB_TMR_LARGE_OFF);
177 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
181 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
182 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
183 pin_reg &= ~DB_TMR_OUT_MASK;
184 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
186 writel(pin_reg, gpio_dev->base + offset * 4);
195 u32 pin_reg;
242 pin_reg = readl(gpio_dev->base + i * 4);
245 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
246 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
254 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
260 if (pin_reg & BIT(LEVEL_TRIG_OFF))
272 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
279 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
284 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
289 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
294 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
296 if (pin_reg & BIT(PULL_UP_SEL_OFF))
305 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
310 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
313 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
321 if (pin_reg & BIT(PIN_STS_OFF))
333 output_value, output_enable, pin_reg);
343 u32 pin_reg;
349 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
350 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
351 pin_reg |= BIT(INTERRUPT_MASK_OFF);
352 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
358 u32 pin_reg;
364 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
365 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
366 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
367 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
373 u32 pin_reg;
379 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
380 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
381 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
387 u32 pin_reg;
393 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
394 pin_reg |= BIT(INTERRUPT_MASK_OFF);
395 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
416 u32 pin_reg, pin_reg_irq_en, mask;
422 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
426 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
427 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
428 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
433 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
434 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
435 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
440 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
441 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
442 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
447 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
448 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
449 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
454 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
455 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
456 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
468 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
485 pin_reg_irq_en = pin_reg;
491 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
629 u32 pin_reg;
636 pin_reg = readl(gpio_dev->base + pin*4);
640 arg = pin_reg & DB_TMR_OUT_MASK;
644 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
648 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
652 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
672 u32 pin_reg;
681 pin_reg = readl(gpio_dev->base + pin*4);
685 pin_reg &= ~DB_TMR_OUT_MASK;
686 pin_reg |= arg & DB_TMR_OUT_MASK;
690 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
691 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
695 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
696 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
697 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
698 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
702 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
704 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
714 writel(pin_reg, gpio_dev->base + pin*4);
782 u32 pin_reg, mask;
798 pin_reg = readl(gpio_dev->base + pin * 4);
799 pin_reg &= ~mask;
800 writel(pin_reg, gpio_dev->base + pin * 4);