Lines Matching refs:base
77 void __iomem *base;
134 bank->gc.base / bank->gc.ngpio,
135 bank->gc.base,
136 bank->gc.base + bank->gc.ngpio);
138 ioread32(bank->base + NPCM7XX_GP_N_DIN),
139 ioread32(bank->base + NPCM7XX_GP_N_DOUT),
140 ioread32(bank->base + NPCM7XX_GP_N_IEM),
141 ioread32(bank->base + NPCM7XX_GP_N_OE));
143 ioread32(bank->base + NPCM7XX_GP_N_PU),
144 ioread32(bank->base + NPCM7XX_GP_N_PD),
145 ioread32(bank->base + NPCM7XX_GP_N_DBNC),
146 ioread32(bank->base + NPCM7XX_GP_N_POL));
148 ioread32(bank->base + NPCM7XX_GP_N_EVTYP),
149 ioread32(bank->base + NPCM7XX_GP_N_EVBE),
150 ioread32(bank->base + NPCM7XX_GP_N_EVEN),
151 ioread32(bank->base + NPCM7XX_GP_N_EVST));
153 ioread32(bank->base + NPCM7XX_GP_N_OTYP),
154 ioread32(bank->base + NPCM7XX_GP_N_OSRC),
155 ioread32(bank->base + NPCM7XX_GP_N_ODSC));
157 ioread32(bank->base + NPCM7XX_GP_N_OBL0),
158 ioread32(bank->base + NPCM7XX_GP_N_OBL1),
159 ioread32(bank->base + NPCM7XX_GP_N_OBL2),
160 ioread32(bank->base + NPCM7XX_GP_N_OBL3));
162 ioread32(bank->base + NPCM7XX_GP_N_SPLCK),
163 ioread32(bank->base + NPCM7XX_GP_N_MPLCK));
171 ret = pinctrl_gpio_direction_input(offset + chip->base);
188 ret = pinctrl_gpio_direction_output(offset + chip->base);
201 ret = pinctrl_gpio_request(offset + chip->base);
211 pinctrl_gpio_free(offset + chip->base);
226 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
227 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
248 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
249 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
253 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
254 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
258 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
262 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
266 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
274 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
278 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
292 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);
304 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);
316 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);
1448 return ioread32(bank->base + NPCM7XX_GP_N_OSRC)
1469 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
1473 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
1514 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)
1540 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1545 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1696 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1698 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1730 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;
1731 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;
1741 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
1742 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
1749 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);
1752 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;
1755 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;
1789 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1790 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1793 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1794 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1797 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1798 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1801 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1805 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1809 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1812 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1815 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);
1878 pctrl->gpio_bank[id].base =
1891 pctrl->gpio_bank[id].base +
1893 pctrl->gpio_bank[id].base +
1897 pctrl->gpio_bank[id].base +
1921 pctrl->gpio_bank[id].gc.base = pinspec.args[1];
1983 pctrl->gpio_bank[id].gc.base,